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[/] [pci/] [tags/] [rel_11/] - Rev 87

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Rev Log message Author Age Path
87 Updated acording to RTL changes. mihad 7777d 21h /pci/tags/rel_11/
86 Entered the option to disable no response counter in wb master. mihad 7777d 21h /pci/tags/rel_11/
85 Changed Vendor ID defines. mihad 7778d 01h /pci/tags/rel_11/
84 Changed vendor ID. mihad 7781d 20h /pci/tags/rel_11/
83 Cleaned up the code. No functional changes. mihad 7806d 18h /pci/tags/rel_11/
81 Updated synchronization in top level fifo modules. mihad 7820d 14h /pci/tags/rel_11/
79 Updated. mihad 7823d 19h /pci/tags/rel_11/
78 Old files with wrong names removed. mihad 7823d 20h /pci/tags/rel_11/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7823d 20h /pci/tags/rel_11/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7826d 19h /pci/tags/rel_11/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7829d 20h /pci/tags/rel_11/
73 Bug fixes, testcases added. mihad 7829d 20h /pci/tags/rel_11/
72 *** empty log message *** mihad 7877d 00h /pci/tags/rel_11/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7884d 16h /pci/tags/rel_11/
69 Changed BIST signal names etc.. mihad 7921d 23h /pci/tags/rel_11/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7925d 09h /pci/tags/rel_11/
67 Changed BIST signals for RAMs. tadejm 7925d 14h /pci/tags/rel_11/
66 Changed empty status generation in pciw_fifo_control.v mihad 7929d 00h /pci/tags/rel_11/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7931d 22h /pci/tags/rel_11/
64 The testcase I just added in previous revision repaired mihad 7932d 00h /pci/tags/rel_11/
63 Added additional testcase and changed rst name in BIST to trst mihad 7932d 02h /pci/tags/rel_11/
62 Added BIST signals for RAMs. mihad 7934d 19h /pci/tags/rel_11/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7942d 19h /pci/tags/rel_11/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7942d 20h /pci/tags/rel_11/
58 Removed all logic from asynchronous reset network mihad 7947d 21h /pci/tags/rel_11/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7948d 03h /pci/tags/rel_11/
56 Number of state bits define was removed mihad 7948d 17h /pci/tags/rel_11/
55 Changed state machine encoding to true one-hot mihad 7948d 18h /pci/tags/rel_11/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7981d 20h /pci/tags/rel_11/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7981d 23h /pci/tags/rel_11/

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