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[/] [pci/] [tags/] [rel_11/] [bench/] [verilog/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5595d 02h /pci/tags/rel_11/bench/verilog/
127 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7520d 19h /pci/tags/rel_11/bench/verilog/
122 mbist signals updated according to newest convention markom 7566d 02h /pci/tags/rel_11/bench/verilog/
119 Added support for WB B3. Some testcases were updated. tadejm 7622d 14h /pci/tags/rel_11/bench/verilog/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7635d 18h /pci/tags/rel_11/bench/verilog/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7640d 17h /pci/tags/rel_11/bench/verilog/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7646d 03h /pci/tags/rel_11/bench/verilog/
92 Update! mihad 7693d 08h /pci/tags/rel_11/bench/verilog/
89 Burst 2 error fixed. mihad 7764d 23h /pci/tags/rel_11/bench/verilog/
87 Updated acording to RTL changes. mihad 7782d 19h /pci/tags/rel_11/bench/verilog/
81 Updated synchronization in top level fifo modules. mihad 7825d 13h /pci/tags/rel_11/bench/verilog/
73 Bug fixes, testcases added. mihad 7834d 19h /pci/tags/rel_11/bench/verilog/
69 Changed BIST signal names etc.. mihad 7926d 22h /pci/tags/rel_11/bench/verilog/
66 Changed empty status generation in pciw_fifo_control.v mihad 7933d 22h /pci/tags/rel_11/bench/verilog/
64 The testcase I just added in previous revision repaired mihad 7936d 23h /pci/tags/rel_11/bench/verilog/
63 Added additional testcase and changed rst name in BIST to trst mihad 7937d 01h /pci/tags/rel_11/bench/verilog/
62 Added BIST signals for RAMs. mihad 7939d 18h /pci/tags/rel_11/bench/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7953d 01h /pci/tags/rel_11/bench/verilog/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7986d 18h /pci/tags/rel_11/bench/verilog/
52 Oops, never before noticed that OC header is missing mihad 7987d 02h /pci/tags/rel_11/bench/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7987d 02h /pci/tags/rel_11/bench/verilog/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7996d 00h /pci/tags/rel_11/bench/verilog/
44 Added for testing of Configuration Cycles Type 1 mihad 7996d 00h /pci/tags/rel_11/bench/verilog/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7996d 00h /pci/tags/rel_11/bench/verilog/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8141d 03h /pci/tags/rel_11/bench/verilog/
34 Added missing include statements mihad 8156d 02h /pci/tags/rel_11/bench/verilog/
33 Added some testcases, removed un-needed fifo signals mihad 8156d 23h /pci/tags/rel_11/bench/verilog/
26 Modified testbench and fixed some bugs mihad 8170d 18h /pci/tags/rel_11/bench/verilog/
19 *** empty log message *** mihad 8188d 20h /pci/tags/rel_11/bench/verilog/
15 Initial testbench import. Still under development mihad 8188d 21h /pci/tags/rel_11/bench/verilog/

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