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[/] [pci/] [tags/] [rel_12/] - Rev 86

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Rev Log message Author Age Path
86 Entered the option to disable no response counter in wb master. mihad 7776d 19h /pci/tags/rel_12/
85 Changed Vendor ID defines. mihad 7776d 23h /pci/tags/rel_12/
84 Changed vendor ID. mihad 7780d 17h /pci/tags/rel_12/
83 Cleaned up the code. No functional changes. mihad 7805d 16h /pci/tags/rel_12/
81 Updated synchronization in top level fifo modules. mihad 7819d 12h /pci/tags/rel_12/
79 Updated. mihad 7822d 17h /pci/tags/rel_12/
78 Old files with wrong names removed. mihad 7822d 18h /pci/tags/rel_12/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7822d 18h /pci/tags/rel_12/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7825d 17h /pci/tags/rel_12/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7828d 18h /pci/tags/rel_12/
73 Bug fixes, testcases added. mihad 7828d 18h /pci/tags/rel_12/
72 *** empty log message *** mihad 7875d 22h /pci/tags/rel_12/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7883d 14h /pci/tags/rel_12/
69 Changed BIST signal names etc.. mihad 7920d 21h /pci/tags/rel_12/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7924d 07h /pci/tags/rel_12/
67 Changed BIST signals for RAMs. tadejm 7924d 12h /pci/tags/rel_12/
66 Changed empty status generation in pciw_fifo_control.v mihad 7927d 22h /pci/tags/rel_12/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7930d 20h /pci/tags/rel_12/
64 The testcase I just added in previous revision repaired mihad 7930d 22h /pci/tags/rel_12/
63 Added additional testcase and changed rst name in BIST to trst mihad 7931d 00h /pci/tags/rel_12/
62 Added BIST signals for RAMs. mihad 7933d 17h /pci/tags/rel_12/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7941d 17h /pci/tags/rel_12/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7941d 18h /pci/tags/rel_12/
58 Removed all logic from asynchronous reset network mihad 7946d 18h /pci/tags/rel_12/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7947d 00h /pci/tags/rel_12/
56 Number of state bits define was removed mihad 7947d 15h /pci/tags/rel_12/
55 Changed state machine encoding to true one-hot mihad 7947d 16h /pci/tags/rel_12/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7980d 17h /pci/tags/rel_12/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7980d 21h /pci/tags/rel_12/
52 Oops, never before noticed that OC header is missing mihad 7981d 01h /pci/tags/rel_12/

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