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[/] [pci/] [tags/] [rel_12/] - Rev 95

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Rev	Log message	Author	Age	Path
95	Removed this file, because it was too large - long download time.	mihad	7684d 18h	/pci/tags/rel_12/
94	Changed one critical PCI bus signal logic.	mihad	7684d 18h	/pci/tags/rel_12/
93	Added a test application!	mihad	7685d 02h	/pci/tags/rel_12/
92	Update!	mihad	7685d 02h	/pci/tags/rel_12/
91	WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7720d 16h	/pci/tags/rel_12/
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7720d 16h	/pci/tags/rel_12/
89	Burst 2 error fixed.	mihad	7756d 16h	/pci/tags/rel_12/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7762d 15h	/pci/tags/rel_12/
87	Updated acording to RTL changes.	mihad	7774d 13h	/pci/tags/rel_12/
86	Entered the option to disable no response counter in wb master.	mihad	7774d 13h	/pci/tags/rel_12/
85	Changed Vendor ID defines.	mihad	7774d 17h	/pci/tags/rel_12/
84	Changed vendor ID.	mihad	7778d 12h	/pci/tags/rel_12/
83	Cleaned up the code. No functional changes.	mihad	7803d 10h	/pci/tags/rel_12/
81	Updated synchronization in top level fifo modules.	mihad	7817d 07h	/pci/tags/rel_12/
79	Updated.	mihad	7820d 12h	/pci/tags/rel_12/
78	Old files with wrong names removed.	mihad	7820d 12h	/pci/tags/rel_12/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7820d 12h	/pci/tags/rel_12/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7823d 11h	/pci/tags/rel_12/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7826d 12h	/pci/tags/rel_12/
73	Bug fixes, testcases added.	mihad	7826d 13h	/pci/tags/rel_12/
72	* empty log message *	mihad	7873d 16h	/pci/tags/rel_12/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7881d 08h	/pci/tags/rel_12/
69	Changed BIST signal names etc..	mihad	7918d 16h	/pci/tags/rel_12/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7922d 01h	/pci/tags/rel_12/
67	Changed BIST signals for RAMs.	tadejm	7922d 06h	/pci/tags/rel_12/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7925d 16h	/pci/tags/rel_12/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7928d 14h	/pci/tags/rel_12/
64	The testcase I just added in previous revision repaired	mihad	7928d 17h	/pci/tags/rel_12/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7928d 19h	/pci/tags/rel_12/
62	Added BIST signals for RAMs.	mihad	7931d 11h	/pci/tags/rel_12/

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[/] [pci/] [tags/] [rel_12/] - Rev 95

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