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[/] [pci/] [tags/] [rel_12/] [rtl/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5621d 19h /pci/tags/rel_12/rtl/
129 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7539d 18h /pci/tags/rel_12/rtl/
128 Some warning cleanup. simons 7539d 18h /pci/tags/rel_12/rtl/
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7547d 11h /pci/tags/rel_12/rtl/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7585d 18h /pci/tags/rel_12/rtl/
122 mbist signals updated according to newest convention markom 7592d 19h /pci/tags/rel_12/rtl/
117 WB Master is now WISHBONE B3 compatible. tadejm 7649d 07h /pci/tags/rel_12/rtl/
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7649d 07h /pci/tags/rel_12/rtl/
115 Added signals for WB Master B3. tadejm 7649d 07h /pci/tags/rel_12/rtl/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7656d 10h /pci/tags/rel_12/rtl/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7656d 15h /pci/tags/rel_12/rtl/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7658d 14h /pci/tags/rel_12/rtl/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7662d 11h /pci/tags/rel_12/rtl/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7667d 10h /pci/tags/rel_12/rtl/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7672d 19h /pci/tags/rel_12/rtl/
94 Changed one critical PCI bus signal logic. mihad 7719d 18h /pci/tags/rel_12/rtl/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7797d 14h /pci/tags/rel_12/rtl/
86 Entered the option to disable no response counter in wb master. mihad 7809d 12h /pci/tags/rel_12/rtl/
83 Cleaned up the code. No functional changes. mihad 7838d 09h /pci/tags/rel_12/rtl/
81 Updated synchronization in top level fifo modules. mihad 7852d 06h /pci/tags/rel_12/rtl/
79 Updated. mihad 7855d 11h /pci/tags/rel_12/rtl/
78 Old files with wrong names removed. mihad 7855d 11h /pci/tags/rel_12/rtl/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7855d 11h /pci/tags/rel_12/rtl/
73 Bug fixes, testcases added. mihad 7861d 12h /pci/tags/rel_12/rtl/
72 *** empty log message *** mihad 7908d 15h /pci/tags/rel_12/rtl/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7916d 07h /pci/tags/rel_12/rtl/
69 Changed BIST signal names etc.. mihad 7953d 15h /pci/tags/rel_12/rtl/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7957d 00h /pci/tags/rel_12/rtl/
67 Changed BIST signals for RAMs. tadejm 7957d 05h /pci/tags/rel_12/rtl/
66 Changed empty status generation in pciw_fifo_control.v mihad 7960d 15h /pci/tags/rel_12/rtl/

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