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[/] [pci/] [tags/] [rel_12/] [rtl/] - Rev 88

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Rev	Log message	Author	Age	Path
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7855d 04h	/pci/tags/rel_12/rtl/
86	Entered the option to disable no response counter in wb master.	mihad	7867d 02h	/pci/tags/rel_12/rtl/
83	Cleaned up the code. No functional changes.	mihad	7895d 23h	/pci/tags/rel_12/rtl/
81	Updated synchronization in top level fifo modules.	mihad	7909d 19h	/pci/tags/rel_12/rtl/
79	Updated.	mihad	7913d 00h	/pci/tags/rel_12/rtl/
78	Old files with wrong names removed.	mihad	7913d 00h	/pci/tags/rel_12/rtl/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7913d 00h	/pci/tags/rel_12/rtl/
73	Bug fixes, testcases added.	mihad	7919d 01h	/pci/tags/rel_12/rtl/
72	* empty log message *	mihad	7966d 05h	/pci/tags/rel_12/rtl/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7973d 21h	/pci/tags/rel_12/rtl/
69	Changed BIST signal names etc..	mihad	8011d 04h	/pci/tags/rel_12/rtl/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	8014d 14h	/pci/tags/rel_12/rtl/
67	Changed BIST signals for RAMs.	tadejm	8014d 18h	/pci/tags/rel_12/rtl/
66	Changed empty status generation in pciw_fifo_control.v	mihad	8018d 05h	/pci/tags/rel_12/rtl/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8021d 03h	/pci/tags/rel_12/rtl/
63	Added additional testcase and changed rst name in BIST to trst	mihad	8021d 07h	/pci/tags/rel_12/rtl/
62	Added BIST signals for RAMs.	mihad	8024d 00h	/pci/tags/rel_12/rtl/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8032d 00h	/pci/tags/rel_12/rtl/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8032d 01h	/pci/tags/rel_12/rtl/
58	Removed all logic from asynchronous reset network	mihad	8037d 01h	/pci/tags/rel_12/rtl/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8037d 07h	/pci/tags/rel_12/rtl/
56	Number of state bits define was removed	mihad	8037d 22h	/pci/tags/rel_12/rtl/
55	Changed state machine encoding to true one-hot	mihad	8037d 23h	/pci/tags/rel_12/rtl/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8071d 04h	/pci/tags/rel_12/rtl/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8071d 08h	/pci/tags/rel_12/rtl/
50	Got rid of undef directives	mihad	8074d 00h	/pci/tags/rel_12/rtl/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8074d 00h	/pci/tags/rel_12/rtl/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8074d 00h	/pci/tags/rel_12/rtl/
47	Known issues repaired	mihad	8074d 06h	/pci/tags/rel_12/rtl/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8079d 01h	/pci/tags/rel_12/rtl/

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[/] [pci/] [tags/] [rel_12/] [rtl/] - Rev 88

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