OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_13/] - Rev 88

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7783d 15h /pci/tags/rel_13/
87 Updated acording to RTL changes. mihad 7795d 13h /pci/tags/rel_13/
86 Entered the option to disable no response counter in wb master. mihad 7795d 13h /pci/tags/rel_13/
85 Changed Vendor ID defines. mihad 7795d 17h /pci/tags/rel_13/
84 Changed vendor ID. mihad 7799d 11h /pci/tags/rel_13/
83 Cleaned up the code. No functional changes. mihad 7824d 10h /pci/tags/rel_13/
81 Updated synchronization in top level fifo modules. mihad 7838d 06h /pci/tags/rel_13/
79 Updated. mihad 7841d 11h /pci/tags/rel_13/
78 Old files with wrong names removed. mihad 7841d 12h /pci/tags/rel_13/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7841d 12h /pci/tags/rel_13/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7844d 11h /pci/tags/rel_13/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7847d 12h /pci/tags/rel_13/
73 Bug fixes, testcases added. mihad 7847d 12h /pci/tags/rel_13/
72 *** empty log message *** mihad 7894d 16h /pci/tags/rel_13/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7902d 08h /pci/tags/rel_13/
69 Changed BIST signal names etc.. mihad 7939d 15h /pci/tags/rel_13/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7943d 01h /pci/tags/rel_13/
67 Changed BIST signals for RAMs. tadejm 7943d 06h /pci/tags/rel_13/
66 Changed empty status generation in pciw_fifo_control.v mihad 7946d 16h /pci/tags/rel_13/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7949d 14h /pci/tags/rel_13/
64 The testcase I just added in previous revision repaired mihad 7949d 16h /pci/tags/rel_13/
63 Added additional testcase and changed rst name in BIST to trst mihad 7949d 18h /pci/tags/rel_13/
62 Added BIST signals for RAMs. mihad 7952d 11h /pci/tags/rel_13/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7960d 11h /pci/tags/rel_13/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7960d 12h /pci/tags/rel_13/
58 Removed all logic from asynchronous reset network mihad 7965d 12h /pci/tags/rel_13/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7965d 18h /pci/tags/rel_13/
56 Number of state bits define was removed mihad 7966d 09h /pci/tags/rel_13/
55 Changed state machine encoding to true one-hot mihad 7966d 10h /pci/tags/rel_13/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7999d 11h /pci/tags/rel_13/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.