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[/] [pci/] [tags/] [rel_13/] - Rev 92

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Rev	Log message	Author	Age	Path
92	Update!	mihad	7724d 08h	/pci/tags/rel_13/
91	WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7759d 22h	/pci/tags/rel_13/
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7759d 22h	/pci/tags/rel_13/
89	Burst 2 error fixed.	mihad	7795d 22h	/pci/tags/rel_13/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7801d 21h	/pci/tags/rel_13/
87	Updated acording to RTL changes.	mihad	7813d 19h	/pci/tags/rel_13/
86	Entered the option to disable no response counter in wb master.	mihad	7813d 19h	/pci/tags/rel_13/
85	Changed Vendor ID defines.	mihad	7813d 23h	/pci/tags/rel_13/
84	Changed vendor ID.	mihad	7817d 18h	/pci/tags/rel_13/
83	Cleaned up the code. No functional changes.	mihad	7842d 16h	/pci/tags/rel_13/
81	Updated synchronization in top level fifo modules.	mihad	7856d 13h	/pci/tags/rel_13/
79	Updated.	mihad	7859d 17h	/pci/tags/rel_13/
78	Old files with wrong names removed.	mihad	7859d 18h	/pci/tags/rel_13/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7859d 18h	/pci/tags/rel_13/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7862d 17h	/pci/tags/rel_13/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7865d 18h	/pci/tags/rel_13/
73	Bug fixes, testcases added.	mihad	7865d 18h	/pci/tags/rel_13/
72	* empty log message *	mihad	7912d 22h	/pci/tags/rel_13/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7920d 14h	/pci/tags/rel_13/
69	Changed BIST signal names etc..	mihad	7957d 21h	/pci/tags/rel_13/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7961d 07h	/pci/tags/rel_13/
67	Changed BIST signals for RAMs.	tadejm	7961d 12h	/pci/tags/rel_13/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7964d 22h	/pci/tags/rel_13/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7967d 20h	/pci/tags/rel_13/
64	The testcase I just added in previous revision repaired	mihad	7967d 23h	/pci/tags/rel_13/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7968d 00h	/pci/tags/rel_13/
62	Added BIST signals for RAMs.	mihad	7970d 17h	/pci/tags/rel_13/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7978d 17h	/pci/tags/rel_13/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7978d 19h	/pci/tags/rel_13/
58	Removed all logic from asynchronous reset network	mihad	7983d 19h	/pci/tags/rel_13/

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[/] [pci/] [tags/] [rel_13/] - Rev 92

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