URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_3/] - Rev 55

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Rev	Log message	Author	Age	Path
55	Changed state machine encoding to true one-hot	mihad	7961d 18h	/pci/tags/rel_3/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7994d 20h	/pci/tags/rel_3/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7994d 23h	/pci/tags/rel_3/
52	Oops, never before noticed that OC header is missing	mihad	7995d 03h	/pci/tags/rel_3/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7995d 04h	/pci/tags/rel_3/
50	Got rid of undef directives	mihad	7997d 20h	/pci/tags/rel_3/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7997d 20h	/pci/tags/rel_3/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7997d 20h	/pci/tags/rel_3/
47	Known issues repaired	mihad	7998d 02h	/pci/tags/rel_3/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8002d 20h	/pci/tags/rel_3/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8004d 02h	/pci/tags/rel_3/
44	Added for testing of Configuration Cycles Type 1	mihad	8004d 02h	/pci/tags/rel_3/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	8004d 02h	/pci/tags/rel_3/
42	Removed out of date files	mihad	8016d 03h	/pci/tags/rel_3/
40	From these Wrod files PDF were created - added future improvements	tadej	8094d 17h	/pci/tags/rel_3/
39	File not needed	tadej	8094d 18h	/pci/tags/rel_3/
38	This file is not needed	tadej	8094d 21h	/pci/tags/rel_3/
37	These files are not needed any more	tadej	8094d 21h	/pci/tags/rel_3/
36	* empty log message *	tadej	8094d 22h	/pci/tags/rel_3/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8149d 05h	/pci/tags/rel_3/
34	Added missing include statements	mihad	8164d 03h	/pci/tags/rel_3/
33	Added some testcases, removed un-needed fifo signals	mihad	8165d 01h	/pci/tags/rel_3/
32	Added include statement that was missing and causing errors	mihad	8172d 21h	/pci/tags/rel_3/
31	User defined constants used for Test Application	tadej	8175d 16h	/pci/tags/rel_3/
30	Example of PCI testbench log file	mihad	8176d 01h	/pci/tags/rel_3/
29	Xilinx synthesys log file	tadej	8176d 03h	/pci/tags/rel_3/
28	pci/doc/pci_databook.pdf	tadej	8176d 22h	/pci/tags/rel_3/
27	Modified testbench and fixed some bugs	mihad	8178d 20h	/pci/tags/rel_3/
26	Modified testbench and fixed some bugs	mihad	8178d 20h	/pci/tags/rel_3/
25	* empty log message *	mihad	8196d 19h	/pci/tags/rel_3/

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[/] [pci/] [tags/] [rel_3/] - Rev 55

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