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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] - Rev 60

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Rev	Log message	Author	Age	Path
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7951d 09h	/pci/tags/rel_3/rtl/verilog/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7951d 10h	/pci/tags/rel_3/rtl/verilog/
58	Removed all logic from asynchronous reset network	mihad	7956d 10h	/pci/tags/rel_3/rtl/verilog/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7956d 16h	/pci/tags/rel_3/rtl/verilog/
56	Number of state bits define was removed	mihad	7957d 07h	/pci/tags/rel_3/rtl/verilog/
55	Changed state machine encoding to true one-hot	mihad	7957d 07h	/pci/tags/rel_3/rtl/verilog/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7990d 12h	/pci/tags/rel_3/rtl/verilog/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7990d 17h	/pci/tags/rel_3/rtl/verilog/
50	Got rid of undef directives	mihad	7993d 09h	/pci/tags/rel_3/rtl/verilog/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7993d 09h	/pci/tags/rel_3/rtl/verilog/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7993d 09h	/pci/tags/rel_3/rtl/verilog/
47	Known issues repaired	mihad	7993d 15h	/pci/tags/rel_3/rtl/verilog/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7998d 09h	/pci/tags/rel_3/rtl/verilog/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7999d 15h	/pci/tags/rel_3/rtl/verilog/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8144d 18h	/pci/tags/rel_3/rtl/verilog/
33	Added some testcases, removed un-needed fifo signals	mihad	8160d 14h	/pci/tags/rel_3/rtl/verilog/
32	Added include statement that was missing and causing errors	mihad	8168d 11h	/pci/tags/rel_3/rtl/verilog/
26	Modified testbench and fixed some bugs	mihad	8174d 09h	/pci/tags/rel_3/rtl/verilog/
23	* empty log message *	mihad	8192d 10h	/pci/tags/rel_3/rtl/verilog/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8192d 11h	/pci/tags/rel_3/rtl/verilog/
19	* empty log message *	mihad	8192d 11h	/pci/tags/rel_3/rtl/verilog/
18	* empty log message *	mihad	8192d 11h	/pci/tags/rel_3/rtl/verilog/
7	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8311d 18h	/pci/tags/rel_3/rtl/verilog/
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8311d 18h	/pci/tags/rel_3/rtl/verilog/
2	New project directory structure	mihad	8314d 10h	/pci/tags/rel_3/rtl/verilog/

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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] - Rev 60

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