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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] - Rev 74

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Rev Log message Author Age Path
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7822d 09h /pci/tags/rel_3/rtl/verilog/
73 Bug fixes, testcases added. mihad 7822d 09h /pci/tags/rel_3/rtl/verilog/
72 *** empty log message *** mihad 7869d 13h /pci/tags/rel_3/rtl/verilog/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7877d 05h /pci/tags/rel_3/rtl/verilog/
69 Changed BIST signal names etc.. mihad 7914d 13h /pci/tags/rel_3/rtl/verilog/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7917d 22h /pci/tags/rel_3/rtl/verilog/
67 Changed BIST signals for RAMs. tadejm 7918d 03h /pci/tags/rel_3/rtl/verilog/
66 Changed empty status generation in pciw_fifo_control.v mihad 7921d 13h /pci/tags/rel_3/rtl/verilog/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7924d 11h /pci/tags/rel_3/rtl/verilog/
63 Added additional testcase and changed rst name in BIST to trst mihad 7924d 15h /pci/tags/rel_3/rtl/verilog/
62 Added BIST signals for RAMs. mihad 7927d 08h /pci/tags/rel_3/rtl/verilog/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7935d 08h /pci/tags/rel_3/rtl/verilog/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7935d 10h /pci/tags/rel_3/rtl/verilog/
58 Removed all logic from asynchronous reset network mihad 7940d 10h /pci/tags/rel_3/rtl/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7940d 16h /pci/tags/rel_3/rtl/verilog/
56 Number of state bits define was removed mihad 7941d 06h /pci/tags/rel_3/rtl/verilog/
55 Changed state machine encoding to true one-hot mihad 7941d 07h /pci/tags/rel_3/rtl/verilog/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7974d 12h /pci/tags/rel_3/rtl/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7974d 16h /pci/tags/rel_3/rtl/verilog/
50 Got rid of undef directives mihad 7977d 09h /pci/tags/rel_3/rtl/verilog/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7977d 09h /pci/tags/rel_3/rtl/verilog/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7977d 09h /pci/tags/rel_3/rtl/verilog/
47 Known issues repaired mihad 7977d 15h /pci/tags/rel_3/rtl/verilog/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7982d 09h /pci/tags/rel_3/rtl/verilog/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7983d 15h /pci/tags/rel_3/rtl/verilog/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8128d 18h /pci/tags/rel_3/rtl/verilog/
33 Added some testcases, removed un-needed fifo signals mihad 8144d 14h /pci/tags/rel_3/rtl/verilog/
32 Added include statement that was missing and causing errors mihad 8152d 10h /pci/tags/rel_3/rtl/verilog/
26 Modified testbench and fixed some bugs mihad 8158d 09h /pci/tags/rel_3/rtl/verilog/
23 *** empty log message *** mihad 8176d 10h /pci/tags/rel_3/rtl/verilog/

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