OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] - Rev 43

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7989d 17h /pci/tags/rel_5/
42 Removed out of date files mihad 8001d 17h /pci/tags/rel_5/
40 From these Wrod files PDF were created - added future improvements tadej 8080d 08h /pci/tags/rel_5/
39 File not needed tadej 8080d 09h /pci/tags/rel_5/
38 This file is not needed tadej 8080d 12h /pci/tags/rel_5/
37 These files are not needed any more tadej 8080d 12h /pci/tags/rel_5/
36 *** empty log message *** tadej 8080d 13h /pci/tags/rel_5/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8134d 20h /pci/tags/rel_5/
34 Added missing include statements mihad 8149d 18h /pci/tags/rel_5/
33 Added some testcases, removed un-needed fifo signals mihad 8150d 16h /pci/tags/rel_5/
32 Added include statement that was missing and causing errors mihad 8158d 12h /pci/tags/rel_5/
31 User defined constants used for Test Application tadej 8161d 07h /pci/tags/rel_5/
30 Example of PCI testbench log file mihad 8161d 16h /pci/tags/rel_5/
29 Xilinx synthesys log file tadej 8161d 18h /pci/tags/rel_5/
28 pci/doc/pci_databook.pdf tadej 8162d 13h /pci/tags/rel_5/
27 Modified testbench and fixed some bugs mihad 8164d 11h /pci/tags/rel_5/
26 Modified testbench and fixed some bugs mihad 8164d 11h /pci/tags/rel_5/
25 *** empty log message *** mihad 8182d 10h /pci/tags/rel_5/
24 *** empty log message *** mihad 8182d 10h /pci/tags/rel_5/
23 *** empty log message *** mihad 8182d 12h /pci/tags/rel_5/
22 Added short description for simulation running mihad 8182d 12h /pci/tags/rel_5/
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8182d 12h /pci/tags/rel_5/
20 *** empty log message *** mihad 8182d 12h /pci/tags/rel_5/
19 *** empty log message *** mihad 8182d 12h /pci/tags/rel_5/
18 *** empty log message *** mihad 8182d 13h /pci/tags/rel_5/
17 *** empty log message *** mihad 8182d 14h /pci/tags/rel_5/
16 Import of various scripts for simulation running mihad 8182d 14h /pci/tags/rel_5/
15 Initial testbench import. Still under development mihad 8182d 14h /pci/tags/rel_5/
14 *** empty log message *** mihad 8182d 14h /pci/tags/rel_5/
13 Added separate software directory to the project mihad 8182d 14h /pci/tags/rel_5/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.