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[/] [pci/] [tags/] [rel_5/] - Rev 59

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Rev Log message Author Age Path
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7947d 16h /pci/tags/rel_5/
58 Removed all logic from asynchronous reset network mihad 7952d 16h /pci/tags/rel_5/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7952d 22h /pci/tags/rel_5/
56 Number of state bits define was removed mihad 7953d 13h /pci/tags/rel_5/
55 Changed state machine encoding to true one-hot mihad 7953d 13h /pci/tags/rel_5/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7986d 15h /pci/tags/rel_5/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7986d 18h /pci/tags/rel_5/
52 Oops, never before noticed that OC header is missing mihad 7986d 23h /pci/tags/rel_5/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7986d 23h /pci/tags/rel_5/
50 Got rid of undef directives mihad 7989d 15h /pci/tags/rel_5/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7989d 15h /pci/tags/rel_5/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7989d 15h /pci/tags/rel_5/
47 Known issues repaired mihad 7989d 21h /pci/tags/rel_5/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7994d 15h /pci/tags/rel_5/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7995d 21h /pci/tags/rel_5/
44 Added for testing of Configuration Cycles Type 1 mihad 7995d 21h /pci/tags/rel_5/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7995d 21h /pci/tags/rel_5/
42 Removed out of date files mihad 8007d 22h /pci/tags/rel_5/
40 From these Wrod files PDF were created - added future improvements tadej 8086d 13h /pci/tags/rel_5/
39 File not needed tadej 8086d 13h /pci/tags/rel_5/
38 This file is not needed tadej 8086d 16h /pci/tags/rel_5/
37 These files are not needed any more tadej 8086d 16h /pci/tags/rel_5/
36 *** empty log message *** tadej 8086d 17h /pci/tags/rel_5/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8141d 00h /pci/tags/rel_5/
34 Added missing include statements mihad 8155d 23h /pci/tags/rel_5/
33 Added some testcases, removed un-needed fifo signals mihad 8156d 20h /pci/tags/rel_5/
32 Added include statement that was missing and causing errors mihad 8164d 17h /pci/tags/rel_5/
31 User defined constants used for Test Application tadej 8167d 12h /pci/tags/rel_5/
30 Example of PCI testbench log file mihad 8167d 20h /pci/tags/rel_5/
29 Xilinx synthesys log file tadej 8167d 23h /pci/tags/rel_5/

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