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[/] [pci/] [tags/] [rel_5/] - Rev 66

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Rev Log message Author Age Path
66 Changed empty status generation in pciw_fifo_control.v mihad 7962d 03h /pci/tags/rel_5/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7965d 01h /pci/tags/rel_5/
64 The testcase I just added in previous revision repaired mihad 7965d 04h /pci/tags/rel_5/
63 Added additional testcase and changed rst name in BIST to trst mihad 7965d 05h /pci/tags/rel_5/
62 Added BIST signals for RAMs. mihad 7967d 22h /pci/tags/rel_5/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7975d 22h /pci/tags/rel_5/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7976d 00h /pci/tags/rel_5/
58 Removed all logic from asynchronous reset network mihad 7981d 00h /pci/tags/rel_5/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7981d 06h /pci/tags/rel_5/
56 Number of state bits define was removed mihad 7981d 20h /pci/tags/rel_5/
55 Changed state machine encoding to true one-hot mihad 7981d 21h /pci/tags/rel_5/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8014d 23h /pci/tags/rel_5/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8015d 02h /pci/tags/rel_5/
52 Oops, never before noticed that OC header is missing mihad 8015d 06h /pci/tags/rel_5/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8015d 06h /pci/tags/rel_5/
50 Got rid of undef directives mihad 8017d 23h /pci/tags/rel_5/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8017d 23h /pci/tags/rel_5/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8017d 23h /pci/tags/rel_5/
47 Known issues repaired mihad 8018d 05h /pci/tags/rel_5/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8022d 23h /pci/tags/rel_5/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8024d 05h /pci/tags/rel_5/
44 Added for testing of Configuration Cycles Type 1 mihad 8024d 05h /pci/tags/rel_5/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 8024d 05h /pci/tags/rel_5/
42 Removed out of date files mihad 8036d 05h /pci/tags/rel_5/
40 From these Wrod files PDF were created - added future improvements tadej 8114d 20h /pci/tags/rel_5/
39 File not needed tadej 8114d 21h /pci/tags/rel_5/
38 This file is not needed tadej 8115d 00h /pci/tags/rel_5/
37 These files are not needed any more tadej 8115d 00h /pci/tags/rel_5/
36 *** empty log message *** tadej 8115d 01h /pci/tags/rel_5/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8169d 08h /pci/tags/rel_5/

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