URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] - Rev 75

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7876d 07h	/pci/tags/rel_5/
73	Bug fixes, testcases added.	mihad	7876d 08h	/pci/tags/rel_5/
72	* empty log message *	mihad	7923d 11h	/pci/tags/rel_5/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7931d 03h	/pci/tags/rel_5/
69	Changed BIST signal names etc..	mihad	7968d 11h	/pci/tags/rel_5/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7971d 20h	/pci/tags/rel_5/
67	Changed BIST signals for RAMs.	tadejm	7972d 01h	/pci/tags/rel_5/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7975d 11h	/pci/tags/rel_5/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7978d 10h	/pci/tags/rel_5/
64	The testcase I just added in previous revision repaired	mihad	7978d 12h	/pci/tags/rel_5/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7978d 14h	/pci/tags/rel_5/
62	Added BIST signals for RAMs.	mihad	7981d 06h	/pci/tags/rel_5/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7989d 06h	/pci/tags/rel_5/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7989d 08h	/pci/tags/rel_5/
58	Removed all logic from asynchronous reset network	mihad	7994d 08h	/pci/tags/rel_5/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7994d 14h	/pci/tags/rel_5/
56	Number of state bits define was removed	mihad	7995d 05h	/pci/tags/rel_5/
55	Changed state machine encoding to true one-hot	mihad	7995d 05h	/pci/tags/rel_5/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	8028d 07h	/pci/tags/rel_5/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8028d 10h	/pci/tags/rel_5/
52	Oops, never before noticed that OC header is missing	mihad	8028d 14h	/pci/tags/rel_5/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8028d 15h	/pci/tags/rel_5/
50	Got rid of undef directives	mihad	8031d 07h	/pci/tags/rel_5/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8031d 07h	/pci/tags/rel_5/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8031d 07h	/pci/tags/rel_5/
47	Known issues repaired	mihad	8031d 13h	/pci/tags/rel_5/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8036d 07h	/pci/tags/rel_5/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8037d 13h	/pci/tags/rel_5/
44	Added for testing of Configuration Cycles Type 1	mihad	8037d 13h	/pci/tags/rel_5/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	8037d 13h	/pci/tags/rel_5/

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] - Rev 75

Filtering Options