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[/] [pci/] [tags/] [rel_5/] - Rev 81

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Rev	Log message	Author	Age	Path
81	Updated synchronization in top level fifo modules.	mihad	7819d 21h	/pci/tags/rel_5/
79	Updated.	mihad	7823d 01h	/pci/tags/rel_5/
78	Old files with wrong names removed.	mihad	7823d 02h	/pci/tags/rel_5/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7823d 02h	/pci/tags/rel_5/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7826d 01h	/pci/tags/rel_5/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7829d 02h	/pci/tags/rel_5/
73	Bug fixes, testcases added.	mihad	7829d 02h	/pci/tags/rel_5/
72	* empty log message *	mihad	7876d 06h	/pci/tags/rel_5/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7883d 22h	/pci/tags/rel_5/
69	Changed BIST signal names etc..	mihad	7921d 05h	/pci/tags/rel_5/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7924d 15h	/pci/tags/rel_5/
67	Changed BIST signals for RAMs.	tadejm	7924d 20h	/pci/tags/rel_5/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7928d 06h	/pci/tags/rel_5/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7931d 04h	/pci/tags/rel_5/
64	The testcase I just added in previous revision repaired	mihad	7931d 06h	/pci/tags/rel_5/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7931d 08h	/pci/tags/rel_5/
62	Added BIST signals for RAMs.	mihad	7934d 01h	/pci/tags/rel_5/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7942d 01h	/pci/tags/rel_5/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7942d 02h	/pci/tags/rel_5/
58	Removed all logic from asynchronous reset network	mihad	7947d 03h	/pci/tags/rel_5/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7947d 09h	/pci/tags/rel_5/
56	Number of state bits define was removed	mihad	7947d 23h	/pci/tags/rel_5/
55	Changed state machine encoding to true one-hot	mihad	7948d 00h	/pci/tags/rel_5/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7981d 02h	/pci/tags/rel_5/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7981d 05h	/pci/tags/rel_5/
52	Oops, never before noticed that OC header is missing	mihad	7981d 09h	/pci/tags/rel_5/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7981d 09h	/pci/tags/rel_5/
50	Got rid of undef directives	mihad	7984d 02h	/pci/tags/rel_5/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7984d 02h	/pci/tags/rel_5/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7984d 02h	/pci/tags/rel_5/

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[/] [pci/] [tags/] [rel_5/] - Rev 81

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