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[/] [pci/] [tags/] [rel_5/] [rtl/] - Rev 66

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Rev	Log message	Author	Age	Path
66	Changed empty status generation in pciw_fifo_control.v	mihad	7926d 01h	/pci/tags/rel_5/rtl/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7928d 23h	/pci/tags/rel_5/rtl/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7929d 03h	/pci/tags/rel_5/rtl/
62	Added BIST signals for RAMs.	mihad	7931d 20h	/pci/tags/rel_5/rtl/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7939d 20h	/pci/tags/rel_5/rtl/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7939d 21h	/pci/tags/rel_5/rtl/
58	Removed all logic from asynchronous reset network	mihad	7944d 21h	/pci/tags/rel_5/rtl/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7945d 03h	/pci/tags/rel_5/rtl/
56	Number of state bits define was removed	mihad	7945d 18h	/pci/tags/rel_5/rtl/
55	Changed state machine encoding to true one-hot	mihad	7945d 19h	/pci/tags/rel_5/rtl/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7979d 00h	/pci/tags/rel_5/rtl/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7979d 04h	/pci/tags/rel_5/rtl/
50	Got rid of undef directives	mihad	7981d 20h	/pci/tags/rel_5/rtl/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7981d 21h	/pci/tags/rel_5/rtl/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7981d 21h	/pci/tags/rel_5/rtl/
47	Known issues repaired	mihad	7982d 02h	/pci/tags/rel_5/rtl/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7986d 21h	/pci/tags/rel_5/rtl/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7988d 02h	/pci/tags/rel_5/rtl/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8133d 06h	/pci/tags/rel_5/rtl/
33	Added some testcases, removed un-needed fifo signals	mihad	8149d 01h	/pci/tags/rel_5/rtl/
32	Added include statement that was missing and causing errors	mihad	8156d 22h	/pci/tags/rel_5/rtl/
26	Modified testbench and fixed some bugs	mihad	8162d 21h	/pci/tags/rel_5/rtl/
23	* empty log message *	mihad	8180d 21h	/pci/tags/rel_5/rtl/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8180d 22h	/pci/tags/rel_5/rtl/
19	* empty log message *	mihad	8180d 22h	/pci/tags/rel_5/rtl/
18	* empty log message *	mihad	8180d 23h	/pci/tags/rel_5/rtl/
7	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8300d 05h	/pci/tags/rel_5/rtl/
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8300d 05h	/pci/tags/rel_5/rtl/
2	New project directory structure	mihad	8302d 22h	/pci/tags/rel_5/rtl/

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] [rtl/] - Rev 66

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