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[/] [pci/] [tags/] [rel_5/] [rtl/] - Rev 81

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Rev	Log message	Author	Age	Path
81	Updated synchronization in top level fifo modules.	mihad	7815d 21h	/pci/tags/rel_5/rtl/
79	Updated.	mihad	7819d 02h	/pci/tags/rel_5/rtl/
78	Old files with wrong names removed.	mihad	7819d 03h	/pci/tags/rel_5/rtl/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7819d 03h	/pci/tags/rel_5/rtl/
73	Bug fixes, testcases added.	mihad	7825d 03h	/pci/tags/rel_5/rtl/
72	* empty log message *	mihad	7872d 07h	/pci/tags/rel_5/rtl/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7879d 23h	/pci/tags/rel_5/rtl/
69	Changed BIST signal names etc..	mihad	7917d 06h	/pci/tags/rel_5/rtl/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7920d 16h	/pci/tags/rel_5/rtl/
67	Changed BIST signals for RAMs.	tadejm	7920d 21h	/pci/tags/rel_5/rtl/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7924d 07h	/pci/tags/rel_5/rtl/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7927d 05h	/pci/tags/rel_5/rtl/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7927d 09h	/pci/tags/rel_5/rtl/
62	Added BIST signals for RAMs.	mihad	7930d 02h	/pci/tags/rel_5/rtl/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7938d 02h	/pci/tags/rel_5/rtl/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7938d 03h	/pci/tags/rel_5/rtl/
58	Removed all logic from asynchronous reset network	mihad	7943d 04h	/pci/tags/rel_5/rtl/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7943d 09h	/pci/tags/rel_5/rtl/
56	Number of state bits define was removed	mihad	7944d 00h	/pci/tags/rel_5/rtl/
55	Changed state machine encoding to true one-hot	mihad	7944d 01h	/pci/tags/rel_5/rtl/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7977d 06h	/pci/tags/rel_5/rtl/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7977d 10h	/pci/tags/rel_5/rtl/
50	Got rid of undef directives	mihad	7980d 02h	/pci/tags/rel_5/rtl/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7980d 03h	/pci/tags/rel_5/rtl/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7980d 03h	/pci/tags/rel_5/rtl/
47	Known issues repaired	mihad	7980d 08h	/pci/tags/rel_5/rtl/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7985d 03h	/pci/tags/rel_5/rtl/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7986d 08h	/pci/tags/rel_5/rtl/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8131d 12h	/pci/tags/rel_5/rtl/
33	Added some testcases, removed un-needed fifo signals	mihad	8147d 08h	/pci/tags/rel_5/rtl/

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[/] [pci/] [tags/] [rel_5/] [rtl/] - Rev 81

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