OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] - Rev 60

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7980d 23h /pci/tags/rel_6/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7981d 01h /pci/tags/rel_6/
58 Removed all logic from asynchronous reset network mihad 7986d 01h /pci/tags/rel_6/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7986d 07h /pci/tags/rel_6/
56 Number of state bits define was removed mihad 7986d 21h /pci/tags/rel_6/
55 Changed state machine encoding to true one-hot mihad 7986d 22h /pci/tags/rel_6/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8020d 00h /pci/tags/rel_6/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8020d 03h /pci/tags/rel_6/
52 Oops, never before noticed that OC header is missing mihad 8020d 07h /pci/tags/rel_6/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8020d 08h /pci/tags/rel_6/
50 Got rid of undef directives mihad 8023d 00h /pci/tags/rel_6/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8023d 00h /pci/tags/rel_6/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8023d 00h /pci/tags/rel_6/
47 Known issues repaired mihad 8023d 06h /pci/tags/rel_6/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8028d 00h /pci/tags/rel_6/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8029d 06h /pci/tags/rel_6/
44 Added for testing of Configuration Cycles Type 1 mihad 8029d 06h /pci/tags/rel_6/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 8029d 06h /pci/tags/rel_6/
42 Removed out of date files mihad 8041d 07h /pci/tags/rel_6/
40 From these Wrod files PDF were created - added future improvements tadej 8119d 21h /pci/tags/rel_6/
39 File not needed tadej 8119d 22h /pci/tags/rel_6/
38 This file is not needed tadej 8120d 01h /pci/tags/rel_6/
37 These files are not needed any more tadej 8120d 01h /pci/tags/rel_6/
36 *** empty log message *** tadej 8120d 02h /pci/tags/rel_6/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8174d 09h /pci/tags/rel_6/
34 Added missing include statements mihad 8189d 07h /pci/tags/rel_6/
33 Added some testcases, removed un-needed fifo signals mihad 8190d 05h /pci/tags/rel_6/
32 Added include statement that was missing and causing errors mihad 8198d 01h /pci/tags/rel_6/
31 User defined constants used for Test Application tadej 8200d 20h /pci/tags/rel_6/
30 Example of PCI testbench log file mihad 8201d 05h /pci/tags/rel_6/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.