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[/] [pci/] [tags/] [rel_6/] - Rev 69

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Rev Log message Author Age Path
69 Changed BIST signal names etc.. mihad 7919d 11h /pci/tags/rel_6/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7922d 21h /pci/tags/rel_6/
67 Changed BIST signals for RAMs. tadejm 7923d 01h /pci/tags/rel_6/
66 Changed empty status generation in pciw_fifo_control.v mihad 7926d 12h /pci/tags/rel_6/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7929d 10h /pci/tags/rel_6/
64 The testcase I just added in previous revision repaired mihad 7929d 12h /pci/tags/rel_6/
63 Added additional testcase and changed rst name in BIST to trst mihad 7929d 14h /pci/tags/rel_6/
62 Added BIST signals for RAMs. mihad 7932d 07h /pci/tags/rel_6/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7940d 07h /pci/tags/rel_6/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7940d 08h /pci/tags/rel_6/
58 Removed all logic from asynchronous reset network mihad 7945d 08h /pci/tags/rel_6/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7945d 14h /pci/tags/rel_6/
56 Number of state bits define was removed mihad 7946d 05h /pci/tags/rel_6/
55 Changed state machine encoding to true one-hot mihad 7946d 06h /pci/tags/rel_6/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7979d 07h /pci/tags/rel_6/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7979d 11h /pci/tags/rel_6/
52 Oops, never before noticed that OC header is missing mihad 7979d 15h /pci/tags/rel_6/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7979d 15h /pci/tags/rel_6/
50 Got rid of undef directives mihad 7982d 07h /pci/tags/rel_6/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7982d 07h /pci/tags/rel_6/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7982d 07h /pci/tags/rel_6/
47 Known issues repaired mihad 7982d 13h /pci/tags/rel_6/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7987d 08h /pci/tags/rel_6/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7988d 13h /pci/tags/rel_6/
44 Added for testing of Configuration Cycles Type 1 mihad 7988d 14h /pci/tags/rel_6/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7988d 14h /pci/tags/rel_6/
42 Removed out of date files mihad 8000d 14h /pci/tags/rel_6/
40 From these Wrod files PDF were created - added future improvements tadej 8079d 05h /pci/tags/rel_6/
39 File not needed tadej 8079d 06h /pci/tags/rel_6/
38 This file is not needed tadej 8079d 08h /pci/tags/rel_6/

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