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[/] [pci/] [tags/] [rel_6/] - Rev 77

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Rev	Log message	Author	Age	Path
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7898d 21h	/pci/tags/rel_6/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7901d 20h	/pci/tags/rel_6/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7904d 21h	/pci/tags/rel_6/
73	Bug fixes, testcases added.	mihad	7904d 21h	/pci/tags/rel_6/
72	* empty log message *	mihad	7952d 01h	/pci/tags/rel_6/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7959d 17h	/pci/tags/rel_6/
69	Changed BIST signal names etc..	mihad	7997d 00h	/pci/tags/rel_6/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	8000d 10h	/pci/tags/rel_6/
67	Changed BIST signals for RAMs.	tadejm	8000d 14h	/pci/tags/rel_6/
66	Changed empty status generation in pciw_fifo_control.v	mihad	8004d 01h	/pci/tags/rel_6/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8006d 23h	/pci/tags/rel_6/
64	The testcase I just added in previous revision repaired	mihad	8007d 01h	/pci/tags/rel_6/
63	Added additional testcase and changed rst name in BIST to trst	mihad	8007d 03h	/pci/tags/rel_6/
62	Added BIST signals for RAMs.	mihad	8009d 20h	/pci/tags/rel_6/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8017d 20h	/pci/tags/rel_6/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8017d 21h	/pci/tags/rel_6/
58	Removed all logic from asynchronous reset network	mihad	8022d 21h	/pci/tags/rel_6/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8023d 03h	/pci/tags/rel_6/
56	Number of state bits define was removed	mihad	8023d 18h	/pci/tags/rel_6/
55	Changed state machine encoding to true one-hot	mihad	8023d 19h	/pci/tags/rel_6/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	8056d 20h	/pci/tags/rel_6/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8057d 00h	/pci/tags/rel_6/
52	Oops, never before noticed that OC header is missing	mihad	8057d 04h	/pci/tags/rel_6/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8057d 04h	/pci/tags/rel_6/
50	Got rid of undef directives	mihad	8059d 20h	/pci/tags/rel_6/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8059d 20h	/pci/tags/rel_6/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8059d 21h	/pci/tags/rel_6/
47	Known issues repaired	mihad	8060d 02h	/pci/tags/rel_6/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8064d 21h	/pci/tags/rel_6/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8066d 02h	/pci/tags/rel_6/

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[/] [pci/] [tags/] [rel_6/] - Rev 77

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