OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [bench/] - Rev 154

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5565d 14h /pci/tags/rel_6/bench/
112 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7600d 09h /pci/tags/rel_6/bench/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7606d 06h /pci/tags/rel_6/bench/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7611d 04h /pci/tags/rel_6/bench/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7616d 14h /pci/tags/rel_6/bench/
92 Update! mihad 7663d 20h /pci/tags/rel_6/bench/
89 Burst 2 error fixed. mihad 7735d 10h /pci/tags/rel_6/bench/
87 Updated acording to RTL changes. mihad 7753d 07h /pci/tags/rel_6/bench/
81 Updated synchronization in top level fifo modules. mihad 7796d 00h /pci/tags/rel_6/bench/
73 Bug fixes, testcases added. mihad 7805d 06h /pci/tags/rel_6/bench/
69 Changed BIST signal names etc.. mihad 7897d 09h /pci/tags/rel_6/bench/
66 Changed empty status generation in pciw_fifo_control.v mihad 7904d 10h /pci/tags/rel_6/bench/
64 The testcase I just added in previous revision repaired mihad 7907d 10h /pci/tags/rel_6/bench/
63 Added additional testcase and changed rst name in BIST to trst mihad 7907d 12h /pci/tags/rel_6/bench/
62 Added BIST signals for RAMs. mihad 7910d 05h /pci/tags/rel_6/bench/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7923d 13h /pci/tags/rel_6/bench/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7957d 06h /pci/tags/rel_6/bench/
52 Oops, never before noticed that OC header is missing mihad 7957d 13h /pci/tags/rel_6/bench/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7957d 13h /pci/tags/rel_6/bench/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7966d 11h /pci/tags/rel_6/bench/
44 Added for testing of Configuration Cycles Type 1 mihad 7966d 12h /pci/tags/rel_6/bench/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7966d 12h /pci/tags/rel_6/bench/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8111d 15h /pci/tags/rel_6/bench/
34 Added missing include statements mihad 8126d 13h /pci/tags/rel_6/bench/
33 Added some testcases, removed un-needed fifo signals mihad 8127d 11h /pci/tags/rel_6/bench/
26 Modified testbench and fixed some bugs mihad 8141d 06h /pci/tags/rel_6/bench/
19 *** empty log message *** mihad 8159d 07h /pci/tags/rel_6/bench/
15 Initial testbench import. Still under development mihad 8159d 09h /pci/tags/rel_6/bench/
3 New project directory structure mihad 8281d 06h /pci/tags/rel_6/bench/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.