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[/] [pci/] [tags/] [rel_6/] [rtl/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5565d 09h /pci/tags/rel_6/rtl/
112 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7600d 05h /pci/tags/rel_6/rtl/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7600d 05h /pci/tags/rel_6/rtl/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7602d 04h /pci/tags/rel_6/rtl/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7606d 01h /pci/tags/rel_6/rtl/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7611d 00h /pci/tags/rel_6/rtl/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7616d 09h /pci/tags/rel_6/rtl/
94 Changed one critical PCI bus signal logic. mihad 7663d 08h /pci/tags/rel_6/rtl/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7741d 04h /pci/tags/rel_6/rtl/
86 Entered the option to disable no response counter in wb master. mihad 7753d 02h /pci/tags/rel_6/rtl/
83 Cleaned up the code. No functional changes. mihad 7781d 23h /pci/tags/rel_6/rtl/
81 Updated synchronization in top level fifo modules. mihad 7795d 20h /pci/tags/rel_6/rtl/
79 Updated. mihad 7799d 01h /pci/tags/rel_6/rtl/
78 Old files with wrong names removed. mihad 7799d 01h /pci/tags/rel_6/rtl/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7799d 01h /pci/tags/rel_6/rtl/
73 Bug fixes, testcases added. mihad 7805d 02h /pci/tags/rel_6/rtl/
72 *** empty log message *** mihad 7852d 05h /pci/tags/rel_6/rtl/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7859d 21h /pci/tags/rel_6/rtl/
69 Changed BIST signal names etc.. mihad 7897d 05h /pci/tags/rel_6/rtl/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7900d 14h /pci/tags/rel_6/rtl/
67 Changed BIST signals for RAMs. tadejm 7900d 19h /pci/tags/rel_6/rtl/
66 Changed empty status generation in pciw_fifo_control.v mihad 7904d 05h /pci/tags/rel_6/rtl/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7907d 03h /pci/tags/rel_6/rtl/
63 Added additional testcase and changed rst name in BIST to trst mihad 7907d 08h /pci/tags/rel_6/rtl/
62 Added BIST signals for RAMs. mihad 7910d 00h /pci/tags/rel_6/rtl/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7918d 00h /pci/tags/rel_6/rtl/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7918d 02h /pci/tags/rel_6/rtl/
58 Removed all logic from asynchronous reset network mihad 7923d 02h /pci/tags/rel_6/rtl/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7923d 08h /pci/tags/rel_6/rtl/
56 Number of state bits define was removed mihad 7923d 23h /pci/tags/rel_6/rtl/

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