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[/] [pci/] [tags/] [rel_7/] - Rev 106

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Rev Log message Author Age Path
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7640d 05h /pci/tags/rel_7/
105 Wrong pci_bridge32.v file included in the project! mihad 7645d 12h /pci/tags/rel_7/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7645d 15h /pci/tags/rel_7/
103 Added test application and modified files to support it. mihad 7692d 12h /pci/tags/rel_7/
102 Cleanup! mihad 7692d 12h /pci/tags/rel_7/
101 Added simulation files. mihad 7692d 12h /pci/tags/rel_7/
100 Cleanup! mihad 7692d 12h /pci/tags/rel_7/
99 Cleanup! mihad 7692d 13h /pci/tags/rel_7/
98 Cleanup. mihad 7692d 13h /pci/tags/rel_7/
97 Doing a little bit of cleanup. mihad 7692d 13h /pci/tags/rel_7/
96 Update! mihad 7692d 13h /pci/tags/rel_7/
95 Removed this file, because it was too large - long download time. mihad 7692d 13h /pci/tags/rel_7/
94 Changed one critical PCI bus signal logic. mihad 7692d 13h /pci/tags/rel_7/
93 Added a test application! mihad 7692d 20h /pci/tags/rel_7/
92 Update! mihad 7692d 21h /pci/tags/rel_7/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7728d 10h /pci/tags/rel_7/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7728d 10h /pci/tags/rel_7/
89 Burst 2 error fixed. mihad 7764d 11h /pci/tags/rel_7/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7770d 10h /pci/tags/rel_7/
87 Updated acording to RTL changes. mihad 7782d 08h /pci/tags/rel_7/
86 Entered the option to disable no response counter in wb master. mihad 7782d 08h /pci/tags/rel_7/
85 Changed Vendor ID defines. mihad 7782d 12h /pci/tags/rel_7/
84 Changed vendor ID. mihad 7786d 06h /pci/tags/rel_7/
83 Cleaned up the code. No functional changes. mihad 7811d 05h /pci/tags/rel_7/
81 Updated synchronization in top level fifo modules. mihad 7825d 01h /pci/tags/rel_7/
79 Updated. mihad 7828d 06h /pci/tags/rel_7/
78 Old files with wrong names removed. mihad 7828d 06h /pci/tags/rel_7/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7828d 06h /pci/tags/rel_7/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7831d 06h /pci/tags/rel_7/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7834d 07h /pci/tags/rel_7/

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