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[/] [pci/] [tags/] [rel_7/] - Rev 114

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Rev Log message Author Age Path
114 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7663d 01h /pci/tags/rel_7/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7663d 01h /pci/tags/rel_7/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7663d 06h /pci/tags/rel_7/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7665d 05h /pci/tags/rel_7/
109 There was missing path to hdl.var file. tadejm 7669d 02h /pci/tags/rel_7/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7669d 02h /pci/tags/rel_7/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7669d 02h /pci/tags/rel_7/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7674d 01h /pci/tags/rel_7/
105 Wrong pci_bridge32.v file included in the project! mihad 7679d 08h /pci/tags/rel_7/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7679d 11h /pci/tags/rel_7/
103 Added test application and modified files to support it. mihad 7726d 08h /pci/tags/rel_7/
102 Cleanup! mihad 7726d 08h /pci/tags/rel_7/
101 Added simulation files. mihad 7726d 08h /pci/tags/rel_7/
100 Cleanup! mihad 7726d 08h /pci/tags/rel_7/
99 Cleanup! mihad 7726d 08h /pci/tags/rel_7/
98 Cleanup. mihad 7726d 08h /pci/tags/rel_7/
97 Doing a little bit of cleanup. mihad 7726d 09h /pci/tags/rel_7/
96 Update! mihad 7726d 09h /pci/tags/rel_7/
95 Removed this file, because it was too large - long download time. mihad 7726d 09h /pci/tags/rel_7/
94 Changed one critical PCI bus signal logic. mihad 7726d 09h /pci/tags/rel_7/
93 Added a test application! mihad 7726d 16h /pci/tags/rel_7/
92 Update! mihad 7726d 16h /pci/tags/rel_7/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7762d 06h /pci/tags/rel_7/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7762d 06h /pci/tags/rel_7/
89 Burst 2 error fixed. mihad 7798d 07h /pci/tags/rel_7/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7804d 06h /pci/tags/rel_7/
87 Updated acording to RTL changes. mihad 7816d 03h /pci/tags/rel_7/
86 Entered the option to disable no response counter in wb master. mihad 7816d 03h /pci/tags/rel_7/
85 Changed Vendor ID defines. mihad 7816d 08h /pci/tags/rel_7/
84 Changed vendor ID. mihad 7820d 02h /pci/tags/rel_7/

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