URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] - Rev 69

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
69	Changed BIST signal names etc..	mihad	7921d 04h	/pci/tags/rel_7/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7924d 13h	/pci/tags/rel_7/
67	Changed BIST signals for RAMs.	tadejm	7924d 18h	/pci/tags/rel_7/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7928d 05h	/pci/tags/rel_7/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7931d 03h	/pci/tags/rel_7/
64	The testcase I just added in previous revision repaired	mihad	7931d 05h	/pci/tags/rel_7/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7931d 07h	/pci/tags/rel_7/
62	Added BIST signals for RAMs.	mihad	7934d 00h	/pci/tags/rel_7/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7942d 00h	/pci/tags/rel_7/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7942d 01h	/pci/tags/rel_7/
58	Removed all logic from asynchronous reset network	mihad	7947d 01h	/pci/tags/rel_7/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7947d 07h	/pci/tags/rel_7/
56	Number of state bits define was removed	mihad	7947d 22h	/pci/tags/rel_7/
55	Changed state machine encoding to true one-hot	mihad	7947d 22h	/pci/tags/rel_7/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7981d 00h	/pci/tags/rel_7/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7981d 04h	/pci/tags/rel_7/
52	Oops, never before noticed that OC header is missing	mihad	7981d 08h	/pci/tags/rel_7/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7981d 08h	/pci/tags/rel_7/
50	Got rid of undef directives	mihad	7984d 00h	/pci/tags/rel_7/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7984d 00h	/pci/tags/rel_7/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7984d 00h	/pci/tags/rel_7/
47	Known issues repaired	mihad	7984d 06h	/pci/tags/rel_7/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7989d 00h	/pci/tags/rel_7/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7990d 06h	/pci/tags/rel_7/
44	Added for testing of Configuration Cycles Type 1	mihad	7990d 06h	/pci/tags/rel_7/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	7990d 06h	/pci/tags/rel_7/
42	Removed out of date files	mihad	8002d 07h	/pci/tags/rel_7/
40	From these Wrod files PDF were created - added future improvements	tadej	8080d 22h	/pci/tags/rel_7/
39	File not needed	tadej	8080d 22h	/pci/tags/rel_7/
38	This file is not needed	tadej	8081d 01h	/pci/tags/rel_7/

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] - Rev 69

Filtering Options