URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] - Rev 91

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
91	WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7748d 14h	/pci/tags/rel_7/
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7748d 14h	/pci/tags/rel_7/
89	Burst 2 error fixed.	mihad	7784d 14h	/pci/tags/rel_7/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7790d 13h	/pci/tags/rel_7/
87	Updated acording to RTL changes.	mihad	7802d 11h	/pci/tags/rel_7/
86	Entered the option to disable no response counter in wb master.	mihad	7802d 11h	/pci/tags/rel_7/
85	Changed Vendor ID defines.	mihad	7802d 15h	/pci/tags/rel_7/
84	Changed vendor ID.	mihad	7806d 10h	/pci/tags/rel_7/
83	Cleaned up the code. No functional changes.	mihad	7831d 08h	/pci/tags/rel_7/
81	Updated synchronization in top level fifo modules.	mihad	7845d 05h	/pci/tags/rel_7/
79	Updated.	mihad	7848d 09h	/pci/tags/rel_7/
78	Old files with wrong names removed.	mihad	7848d 10h	/pci/tags/rel_7/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7848d 10h	/pci/tags/rel_7/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7851d 09h	/pci/tags/rel_7/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7854d 10h	/pci/tags/rel_7/
73	Bug fixes, testcases added.	mihad	7854d 10h	/pci/tags/rel_7/
72	* empty log message *	mihad	7901d 14h	/pci/tags/rel_7/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7909d 06h	/pci/tags/rel_7/
69	Changed BIST signal names etc..	mihad	7946d 14h	/pci/tags/rel_7/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7949d 23h	/pci/tags/rel_7/
67	Changed BIST signals for RAMs.	tadejm	7950d 04h	/pci/tags/rel_7/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7953d 14h	/pci/tags/rel_7/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7956d 12h	/pci/tags/rel_7/
64	The testcase I just added in previous revision repaired	mihad	7956d 15h	/pci/tags/rel_7/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7956d 16h	/pci/tags/rel_7/
62	Added BIST signals for RAMs.	mihad	7959d 09h	/pci/tags/rel_7/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7967d 09h	/pci/tags/rel_7/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7967d 11h	/pci/tags/rel_7/
58	Removed all logic from asynchronous reset network	mihad	7972d 11h	/pci/tags/rel_7/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7972d 17h	/pci/tags/rel_7/

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] - Rev 91

Filtering Options