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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5576d 21h /pci/tags/rel_7/rtl/verilog/
114 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7611d 12h /pci/tags/rel_7/rtl/verilog/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7611d 12h /pci/tags/rel_7/rtl/verilog/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7611d 17h /pci/tags/rel_7/rtl/verilog/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7613d 16h /pci/tags/rel_7/rtl/verilog/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7617d 13h /pci/tags/rel_7/rtl/verilog/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7622d 12h /pci/tags/rel_7/rtl/verilog/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7627d 21h /pci/tags/rel_7/rtl/verilog/
94 Changed one critical PCI bus signal logic. mihad 7674d 19h /pci/tags/rel_7/rtl/verilog/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7752d 16h /pci/tags/rel_7/rtl/verilog/
86 Entered the option to disable no response counter in wb master. mihad 7764d 14h /pci/tags/rel_7/rtl/verilog/
83 Cleaned up the code. No functional changes. mihad 7793d 11h /pci/tags/rel_7/rtl/verilog/
81 Updated synchronization in top level fifo modules. mihad 7807d 08h /pci/tags/rel_7/rtl/verilog/
79 Updated. mihad 7810d 13h /pci/tags/rel_7/rtl/verilog/
78 Old files with wrong names removed. mihad 7810d 13h /pci/tags/rel_7/rtl/verilog/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7810d 13h /pci/tags/rel_7/rtl/verilog/
73 Bug fixes, testcases added. mihad 7816d 14h /pci/tags/rel_7/rtl/verilog/
72 *** empty log message *** mihad 7863d 17h /pci/tags/rel_7/rtl/verilog/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7871d 09h /pci/tags/rel_7/rtl/verilog/
69 Changed BIST signal names etc.. mihad 7908d 17h /pci/tags/rel_7/rtl/verilog/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7912d 02h /pci/tags/rel_7/rtl/verilog/
67 Changed BIST signals for RAMs. tadejm 7912d 07h /pci/tags/rel_7/rtl/verilog/
66 Changed empty status generation in pciw_fifo_control.v mihad 7915d 17h /pci/tags/rel_7/rtl/verilog/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7918d 15h /pci/tags/rel_7/rtl/verilog/
63 Added additional testcase and changed rst name in BIST to trst mihad 7918d 20h /pci/tags/rel_7/rtl/verilog/
62 Added BIST signals for RAMs. mihad 7921d 12h /pci/tags/rel_7/rtl/verilog/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7929d 12h /pci/tags/rel_7/rtl/verilog/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7929d 14h /pci/tags/rel_7/rtl/verilog/
58 Removed all logic from asynchronous reset network mihad 7934d 14h /pci/tags/rel_7/rtl/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7934d 20h /pci/tags/rel_7/rtl/verilog/

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