OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 88

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7763d 21h /pci/tags/rel_7/rtl/verilog/
86 Entered the option to disable no response counter in wb master. mihad 7775d 19h /pci/tags/rel_7/rtl/verilog/
83 Cleaned up the code. No functional changes. mihad 7804d 16h /pci/tags/rel_7/rtl/verilog/
81 Updated synchronization in top level fifo modules. mihad 7818d 12h /pci/tags/rel_7/rtl/verilog/
79 Updated. mihad 7821d 17h /pci/tags/rel_7/rtl/verilog/
78 Old files with wrong names removed. mihad 7821d 17h /pci/tags/rel_7/rtl/verilog/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7821d 17h /pci/tags/rel_7/rtl/verilog/
73 Bug fixes, testcases added. mihad 7827d 18h /pci/tags/rel_7/rtl/verilog/
72 *** empty log message *** mihad 7874d 22h /pci/tags/rel_7/rtl/verilog/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7882d 13h /pci/tags/rel_7/rtl/verilog/
69 Changed BIST signal names etc.. mihad 7919d 21h /pci/tags/rel_7/rtl/verilog/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7923d 06h /pci/tags/rel_7/rtl/verilog/
67 Changed BIST signals for RAMs. tadejm 7923d 11h /pci/tags/rel_7/rtl/verilog/
66 Changed empty status generation in pciw_fifo_control.v mihad 7926d 22h /pci/tags/rel_7/rtl/verilog/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7929d 20h /pci/tags/rel_7/rtl/verilog/
63 Added additional testcase and changed rst name in BIST to trst mihad 7930d 00h /pci/tags/rel_7/rtl/verilog/
62 Added BIST signals for RAMs. mihad 7932d 17h /pci/tags/rel_7/rtl/verilog/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7940d 17h /pci/tags/rel_7/rtl/verilog/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7940d 18h /pci/tags/rel_7/rtl/verilog/
58 Removed all logic from asynchronous reset network mihad 7945d 18h /pci/tags/rel_7/rtl/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7946d 00h /pci/tags/rel_7/rtl/verilog/
56 Number of state bits define was removed mihad 7946d 15h /pci/tags/rel_7/rtl/verilog/
55 Changed state machine encoding to true one-hot mihad 7946d 16h /pci/tags/rel_7/rtl/verilog/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7979d 21h /pci/tags/rel_7/rtl/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7980d 01h /pci/tags/rel_7/rtl/verilog/
50 Got rid of undef directives mihad 7982d 17h /pci/tags/rel_7/rtl/verilog/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7982d 17h /pci/tags/rel_7/rtl/verilog/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7982d 17h /pci/tags/rel_7/rtl/verilog/
47 Known issues repaired mihad 7982d 23h /pci/tags/rel_7/rtl/verilog/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7987d 17h /pci/tags/rel_7/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.