OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] - Rev 101

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
101 Added simulation files. mihad 7687d 02h /pci/tags/rel_8/
100 Cleanup! mihad 7687d 02h /pci/tags/rel_8/
99 Cleanup! mihad 7687d 03h /pci/tags/rel_8/
98 Cleanup. mihad 7687d 03h /pci/tags/rel_8/
97 Doing a little bit of cleanup. mihad 7687d 03h /pci/tags/rel_8/
96 Update! mihad 7687d 03h /pci/tags/rel_8/
95 Removed this file, because it was too large - long download time. mihad 7687d 03h /pci/tags/rel_8/
94 Changed one critical PCI bus signal logic. mihad 7687d 03h /pci/tags/rel_8/
93 Added a test application! mihad 7687d 10h /pci/tags/rel_8/
92 Update! mihad 7687d 11h /pci/tags/rel_8/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7723d 00h /pci/tags/rel_8/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7723d 00h /pci/tags/rel_8/
89 Burst 2 error fixed. mihad 7759d 01h /pci/tags/rel_8/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7765d 00h /pci/tags/rel_8/
87 Updated acording to RTL changes. mihad 7776d 22h /pci/tags/rel_8/
86 Entered the option to disable no response counter in wb master. mihad 7776d 22h /pci/tags/rel_8/
85 Changed Vendor ID defines. mihad 7777d 02h /pci/tags/rel_8/
84 Changed vendor ID. mihad 7780d 20h /pci/tags/rel_8/
83 Cleaned up the code. No functional changes. mihad 7805d 19h /pci/tags/rel_8/
81 Updated synchronization in top level fifo modules. mihad 7819d 15h /pci/tags/rel_8/
79 Updated. mihad 7822d 20h /pci/tags/rel_8/
78 Old files with wrong names removed. mihad 7822d 20h /pci/tags/rel_8/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7822d 20h /pci/tags/rel_8/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7825d 20h /pci/tags/rel_8/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7828d 21h /pci/tags/rel_8/
73 Bug fixes, testcases added. mihad 7828d 21h /pci/tags/rel_8/
72 *** empty log message *** mihad 7876d 01h /pci/tags/rel_8/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7883d 17h /pci/tags/rel_8/
69 Changed BIST signal names etc.. mihad 7921d 00h /pci/tags/rel_8/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7924d 10h /pci/tags/rel_8/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.