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[/] [pci/] [tags/] [rel_8/] - Rev 108

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Rev Log message Author Age Path
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7622d 04h /pci/tags/rel_8/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7622d 04h /pci/tags/rel_8/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7627d 02h /pci/tags/rel_8/
105 Wrong pci_bridge32.v file included in the project! mihad 7632d 09h /pci/tags/rel_8/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7632d 12h /pci/tags/rel_8/
103 Added test application and modified files to support it. mihad 7679d 09h /pci/tags/rel_8/
102 Cleanup! mihad 7679d 09h /pci/tags/rel_8/
101 Added simulation files. mihad 7679d 09h /pci/tags/rel_8/
100 Cleanup! mihad 7679d 09h /pci/tags/rel_8/
99 Cleanup! mihad 7679d 10h /pci/tags/rel_8/
98 Cleanup. mihad 7679d 10h /pci/tags/rel_8/
97 Doing a little bit of cleanup. mihad 7679d 10h /pci/tags/rel_8/
96 Update! mihad 7679d 10h /pci/tags/rel_8/
95 Removed this file, because it was too large - long download time. mihad 7679d 10h /pci/tags/rel_8/
94 Changed one critical PCI bus signal logic. mihad 7679d 10h /pci/tags/rel_8/
93 Added a test application! mihad 7679d 17h /pci/tags/rel_8/
92 Update! mihad 7679d 18h /pci/tags/rel_8/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7715d 07h /pci/tags/rel_8/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7715d 07h /pci/tags/rel_8/
89 Burst 2 error fixed. mihad 7751d 08h /pci/tags/rel_8/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7757d 07h /pci/tags/rel_8/
87 Updated acording to RTL changes. mihad 7769d 05h /pci/tags/rel_8/
86 Entered the option to disable no response counter in wb master. mihad 7769d 05h /pci/tags/rel_8/
85 Changed Vendor ID defines. mihad 7769d 09h /pci/tags/rel_8/
84 Changed vendor ID. mihad 7773d 03h /pci/tags/rel_8/
83 Cleaned up the code. No functional changes. mihad 7798d 02h /pci/tags/rel_8/
81 Updated synchronization in top level fifo modules. mihad 7811d 22h /pci/tags/rel_8/
79 Updated. mihad 7815d 03h /pci/tags/rel_8/
78 Old files with wrong names removed. mihad 7815d 03h /pci/tags/rel_8/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7815d 03h /pci/tags/rel_8/

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