OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] - Rev 117

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
117 WB Master is now WISHBONE B3 compatible. tadejm 7631d 14h /pci/tags/rel_8/
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7631d 14h /pci/tags/rel_8/
115 Added signals for WB Master B3. tadejm 7631d 14h /pci/tags/rel_8/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7638d 17h /pci/tags/rel_8/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7638d 22h /pci/tags/rel_8/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7640d 21h /pci/tags/rel_8/
109 There was missing path to hdl.var file. tadejm 7644d 18h /pci/tags/rel_8/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7644d 19h /pci/tags/rel_8/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7644d 19h /pci/tags/rel_8/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7649d 17h /pci/tags/rel_8/
105 Wrong pci_bridge32.v file included in the project! mihad 7655d 00h /pci/tags/rel_8/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7655d 03h /pci/tags/rel_8/
103 Added test application and modified files to support it. mihad 7702d 00h /pci/tags/rel_8/
102 Cleanup! mihad 7702d 00h /pci/tags/rel_8/
101 Added simulation files. mihad 7702d 00h /pci/tags/rel_8/
100 Cleanup! mihad 7702d 00h /pci/tags/rel_8/
99 Cleanup! mihad 7702d 01h /pci/tags/rel_8/
98 Cleanup. mihad 7702d 01h /pci/tags/rel_8/
97 Doing a little bit of cleanup. mihad 7702d 01h /pci/tags/rel_8/
96 Update! mihad 7702d 01h /pci/tags/rel_8/
95 Removed this file, because it was too large - long download time. mihad 7702d 01h /pci/tags/rel_8/
94 Changed one critical PCI bus signal logic. mihad 7702d 01h /pci/tags/rel_8/
93 Added a test application! mihad 7702d 08h /pci/tags/rel_8/
92 Update! mihad 7702d 09h /pci/tags/rel_8/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7737d 22h /pci/tags/rel_8/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7737d 22h /pci/tags/rel_8/
89 Burst 2 error fixed. mihad 7773d 23h /pci/tags/rel_8/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7779d 22h /pci/tags/rel_8/
87 Updated acording to RTL changes. mihad 7791d 20h /pci/tags/rel_8/
86 Entered the option to disable no response counter in wb master. mihad 7791d 20h /pci/tags/rel_8/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.