URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] - Rev 54

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Rev	Log message	Author	Age	Path
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	8013d 00h	/pci/tags/rel_8/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8013d 04h	/pci/tags/rel_8/
52	Oops, never before noticed that OC header is missing	mihad	8013d 08h	/pci/tags/rel_8/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8013d 08h	/pci/tags/rel_8/
50	Got rid of undef directives	mihad	8016d 00h	/pci/tags/rel_8/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	8016d 00h	/pci/tags/rel_8/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	8016d 00h	/pci/tags/rel_8/
47	Known issues repaired	mihad	8016d 06h	/pci/tags/rel_8/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8021d 01h	/pci/tags/rel_8/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8022d 06h	/pci/tags/rel_8/
44	Added for testing of Configuration Cycles Type 1	mihad	8022d 07h	/pci/tags/rel_8/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	8022d 07h	/pci/tags/rel_8/
42	Removed out of date files	mihad	8034d 07h	/pci/tags/rel_8/
40	From these Wrod files PDF were created - added future improvements	tadej	8112d 22h	/pci/tags/rel_8/
39	File not needed	tadej	8112d 23h	/pci/tags/rel_8/
38	This file is not needed	tadej	8113d 01h	/pci/tags/rel_8/
37	These files are not needed any more	tadej	8113d 02h	/pci/tags/rel_8/
36	* empty log message *	tadej	8113d 02h	/pci/tags/rel_8/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8167d 10h	/pci/tags/rel_8/
34	Added missing include statements	mihad	8182d 08h	/pci/tags/rel_8/
33	Added some testcases, removed un-needed fifo signals	mihad	8183d 05h	/pci/tags/rel_8/
32	Added include statement that was missing and causing errors	mihad	8191d 02h	/pci/tags/rel_8/
31	User defined constants used for Test Application	tadej	8193d 21h	/pci/tags/rel_8/
30	Example of PCI testbench log file	mihad	8194d 05h	/pci/tags/rel_8/
29	Xilinx synthesys log file	tadej	8194d 08h	/pci/tags/rel_8/
28	pci/doc/pci_databook.pdf	tadej	8195d 03h	/pci/tags/rel_8/
27	Modified testbench and fixed some bugs	mihad	8197d 00h	/pci/tags/rel_8/
26	Modified testbench and fixed some bugs	mihad	8197d 01h	/pci/tags/rel_8/
25	* empty log message *	mihad	8214d 23h	/pci/tags/rel_8/
24	* empty log message *	mihad	8215d 00h	/pci/tags/rel_8/

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[/] [pci/] [tags/] [rel_8/] - Rev 54

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