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[/] [pci/] [tags/] [rel_8/] - Rev 73

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Rev Log message Author Age Path
73 Bug fixes, testcases added. mihad 7835d 10h /pci/tags/rel_8/
72 *** empty log message *** mihad 7882d 14h /pci/tags/rel_8/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7890d 05h /pci/tags/rel_8/
69 Changed BIST signal names etc.. mihad 7927d 13h /pci/tags/rel_8/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7930d 22h /pci/tags/rel_8/
67 Changed BIST signals for RAMs. tadejm 7931d 03h /pci/tags/rel_8/
66 Changed empty status generation in pciw_fifo_control.v mihad 7934d 13h /pci/tags/rel_8/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7937d 12h /pci/tags/rel_8/
64 The testcase I just added in previous revision repaired mihad 7937d 14h /pci/tags/rel_8/
63 Added additional testcase and changed rst name in BIST to trst mihad 7937d 16h /pci/tags/rel_8/
62 Added BIST signals for RAMs. mihad 7940d 09h /pci/tags/rel_8/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7948d 08h /pci/tags/rel_8/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7948d 10h /pci/tags/rel_8/
58 Removed all logic from asynchronous reset network mihad 7953d 10h /pci/tags/rel_8/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7953d 16h /pci/tags/rel_8/
56 Number of state bits define was removed mihad 7954d 07h /pci/tags/rel_8/
55 Changed state machine encoding to true one-hot mihad 7954d 07h /pci/tags/rel_8/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7987d 09h /pci/tags/rel_8/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7987d 12h /pci/tags/rel_8/
52 Oops, never before noticed that OC header is missing mihad 7987d 17h /pci/tags/rel_8/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7987d 17h /pci/tags/rel_8/
50 Got rid of undef directives mihad 7990d 09h /pci/tags/rel_8/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7990d 09h /pci/tags/rel_8/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7990d 09h /pci/tags/rel_8/
47 Known issues repaired mihad 7990d 15h /pci/tags/rel_8/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7995d 09h /pci/tags/rel_8/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7996d 15h /pci/tags/rel_8/
44 Added for testing of Configuration Cycles Type 1 mihad 7996d 15h /pci/tags/rel_8/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7996d 15h /pci/tags/rel_8/
42 Removed out of date files mihad 8008d 16h /pci/tags/rel_8/

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