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[/] [pci/] [tags/] [rel_8/] - Rev 81

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Rev Log message Author Age Path
81 Updated synchronization in top level fifo modules. mihad 7824d 23h /pci/tags/rel_8/
79 Updated. mihad 7828d 04h /pci/tags/rel_8/
78 Old files with wrong names removed. mihad 7828d 04h /pci/tags/rel_8/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7828d 04h /pci/tags/rel_8/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7831d 04h /pci/tags/rel_8/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7834d 05h /pci/tags/rel_8/
73 Bug fixes, testcases added. mihad 7834d 05h /pci/tags/rel_8/
72 *** empty log message *** mihad 7881d 09h /pci/tags/rel_8/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7889d 01h /pci/tags/rel_8/
69 Changed BIST signal names etc.. mihad 7926d 08h /pci/tags/rel_8/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7929d 18h /pci/tags/rel_8/
67 Changed BIST signals for RAMs. tadejm 7929d 22h /pci/tags/rel_8/
66 Changed empty status generation in pciw_fifo_control.v mihad 7933d 09h /pci/tags/rel_8/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7936d 07h /pci/tags/rel_8/
64 The testcase I just added in previous revision repaired mihad 7936d 09h /pci/tags/rel_8/
63 Added additional testcase and changed rst name in BIST to trst mihad 7936d 11h /pci/tags/rel_8/
62 Added BIST signals for RAMs. mihad 7939d 04h /pci/tags/rel_8/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7947d 04h /pci/tags/rel_8/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7947d 05h /pci/tags/rel_8/
58 Removed all logic from asynchronous reset network mihad 7952d 05h /pci/tags/rel_8/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7952d 11h /pci/tags/rel_8/
56 Number of state bits define was removed mihad 7953d 02h /pci/tags/rel_8/
55 Changed state machine encoding to true one-hot mihad 7953d 03h /pci/tags/rel_8/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7986d 04h /pci/tags/rel_8/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7986d 08h /pci/tags/rel_8/
52 Oops, never before noticed that OC header is missing mihad 7986d 12h /pci/tags/rel_8/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7986d 12h /pci/tags/rel_8/
50 Got rid of undef directives mihad 7989d 04h /pci/tags/rel_8/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7989d 04h /pci/tags/rel_8/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7989d 04h /pci/tags/rel_8/

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