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[/] [pci/] [tags/] [rel_8/] - Rev 87

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Rev	Log message	Author	Age	Path
87	Updated acording to RTL changes.	mihad	7809d 20h	/pci/tags/rel_8/
86	Entered the option to disable no response counter in wb master.	mihad	7809d 20h	/pci/tags/rel_8/
85	Changed Vendor ID defines.	mihad	7810d 00h	/pci/tags/rel_8/
84	Changed vendor ID.	mihad	7813d 19h	/pci/tags/rel_8/
83	Cleaned up the code. No functional changes.	mihad	7838d 17h	/pci/tags/rel_8/
81	Updated synchronization in top level fifo modules.	mihad	7852d 14h	/pci/tags/rel_8/
79	Updated.	mihad	7855d 19h	/pci/tags/rel_8/
78	Old files with wrong names removed.	mihad	7855d 19h	/pci/tags/rel_8/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7855d 19h	/pci/tags/rel_8/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7858d 18h	/pci/tags/rel_8/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7861d 19h	/pci/tags/rel_8/
73	Bug fixes, testcases added.	mihad	7861d 20h	/pci/tags/rel_8/
72	* empty log message *	mihad	7908d 23h	/pci/tags/rel_8/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7916d 15h	/pci/tags/rel_8/
69	Changed BIST signal names etc..	mihad	7953d 23h	/pci/tags/rel_8/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7957d 08h	/pci/tags/rel_8/
67	Changed BIST signals for RAMs.	tadejm	7957d 13h	/pci/tags/rel_8/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7960d 23h	/pci/tags/rel_8/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7963d 21h	/pci/tags/rel_8/
64	The testcase I just added in previous revision repaired	mihad	7964d 00h	/pci/tags/rel_8/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7964d 02h	/pci/tags/rel_8/
62	Added BIST signals for RAMs.	mihad	7966d 18h	/pci/tags/rel_8/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7974d 18h	/pci/tags/rel_8/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7974d 20h	/pci/tags/rel_8/
58	Removed all logic from asynchronous reset network	mihad	7979d 20h	/pci/tags/rel_8/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7980d 02h	/pci/tags/rel_8/
56	Number of state bits define was removed	mihad	7980d 17h	/pci/tags/rel_8/
55	Changed state machine encoding to true one-hot	mihad	7980d 17h	/pci/tags/rel_8/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	8013d 19h	/pci/tags/rel_8/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8013d 22h	/pci/tags/rel_8/

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[/] [pci/] [tags/] [rel_8/] - Rev 87

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