URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] [bench/] - Rev 106

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Rev	Log message	Author	Age	Path
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7632d 10h	/pci/tags/rel_8/bench/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7637d 20h	/pci/tags/rel_8/bench/
92	Update!	mihad	7685d 01h	/pci/tags/rel_8/bench/
89	Burst 2 error fixed.	mihad	7756d 16h	/pci/tags/rel_8/bench/
87	Updated acording to RTL changes.	mihad	7774d 12h	/pci/tags/rel_8/bench/
81	Updated synchronization in top level fifo modules.	mihad	7817d 06h	/pci/tags/rel_8/bench/
73	Bug fixes, testcases added.	mihad	7826d 12h	/pci/tags/rel_8/bench/
69	Changed BIST signal names etc..	mihad	7918d 15h	/pci/tags/rel_8/bench/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7925d 16h	/pci/tags/rel_8/bench/
64	The testcase I just added in previous revision repaired	mihad	7928d 16h	/pci/tags/rel_8/bench/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7928d 18h	/pci/tags/rel_8/bench/
62	Added BIST signals for RAMs.	mihad	7931d 11h	/pci/tags/rel_8/bench/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7944d 18h	/pci/tags/rel_8/bench/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7978d 11h	/pci/tags/rel_8/bench/
52	Oops, never before noticed that OC header is missing	mihad	7978d 19h	/pci/tags/rel_8/bench/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7978d 19h	/pci/tags/rel_8/bench/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7987d 17h	/pci/tags/rel_8/bench/
44	Added for testing of Configuration Cycles Type 1	mihad	7987d 17h	/pci/tags/rel_8/bench/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	7987d 17h	/pci/tags/rel_8/bench/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8132d 20h	/pci/tags/rel_8/bench/
34	Added missing include statements	mihad	8147d 19h	/pci/tags/rel_8/bench/
33	Added some testcases, removed un-needed fifo signals	mihad	8148d 16h	/pci/tags/rel_8/bench/
26	Modified testbench and fixed some bugs	mihad	8162d 11h	/pci/tags/rel_8/bench/
19	* empty log message *	mihad	8180d 13h	/pci/tags/rel_8/bench/
15	Initial testbench import. Still under development	mihad	8180d 14h	/pci/tags/rel_8/bench/
3	New project directory structure	mihad	8302d 12h	/pci/tags/rel_8/bench/

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] [bench/] - Rev 106

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