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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 103

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Rev Log message Author Age Path
103 Added test application and modified files to support it. mihad 7726d 01h /pci/tags/rel_WB_B3/
102 Cleanup! mihad 7726d 01h /pci/tags/rel_WB_B3/
101 Added simulation files. mihad 7726d 01h /pci/tags/rel_WB_B3/
100 Cleanup! mihad 7726d 01h /pci/tags/rel_WB_B3/
99 Cleanup! mihad 7726d 02h /pci/tags/rel_WB_B3/
98 Cleanup. mihad 7726d 02h /pci/tags/rel_WB_B3/
97 Doing a little bit of cleanup. mihad 7726d 02h /pci/tags/rel_WB_B3/
96 Update! mihad 7726d 02h /pci/tags/rel_WB_B3/
95 Removed this file, because it was too large - long download time. mihad 7726d 02h /pci/tags/rel_WB_B3/
94 Changed one critical PCI bus signal logic. mihad 7726d 02h /pci/tags/rel_WB_B3/
93 Added a test application! mihad 7726d 09h /pci/tags/rel_WB_B3/
92 Update! mihad 7726d 10h /pci/tags/rel_WB_B3/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7761d 23h /pci/tags/rel_WB_B3/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7762d 00h /pci/tags/rel_WB_B3/
89 Burst 2 error fixed. mihad 7798d 00h /pci/tags/rel_WB_B3/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7803d 23h /pci/tags/rel_WB_B3/
87 Updated acording to RTL changes. mihad 7815d 21h /pci/tags/rel_WB_B3/
86 Entered the option to disable no response counter in wb master. mihad 7815d 21h /pci/tags/rel_WB_B3/
85 Changed Vendor ID defines. mihad 7816d 01h /pci/tags/rel_WB_B3/
84 Changed vendor ID. mihad 7819d 19h /pci/tags/rel_WB_B3/
83 Cleaned up the code. No functional changes. mihad 7844d 18h /pci/tags/rel_WB_B3/
81 Updated synchronization in top level fifo modules. mihad 7858d 14h /pci/tags/rel_WB_B3/
79 Updated. mihad 7861d 19h /pci/tags/rel_WB_B3/
78 Old files with wrong names removed. mihad 7861d 19h /pci/tags/rel_WB_B3/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7861d 19h /pci/tags/rel_WB_B3/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7864d 19h /pci/tags/rel_WB_B3/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7867d 20h /pci/tags/rel_WB_B3/
73 Bug fixes, testcases added. mihad 7867d 20h /pci/tags/rel_WB_B3/
72 *** empty log message *** mihad 7915d 00h /pci/tags/rel_WB_B3/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7922d 16h /pci/tags/rel_WB_B3/

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