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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 121

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121 This commit was manufactured by cvs2svn to create tag 'rel_WB_B3'. 7630d 08h /pci/tags/rel_WB_B3/
119 Added support for WB B3. Some testcases were updated. tadejm 7630d 08h /pci/tags/rel_WB_B3/
118 Some minor changes due to changes in core. tadejm 7630d 08h /pci/tags/rel_WB_B3/
117 WB Master is now WISHBONE B3 compatible. tadejm 7630d 08h /pci/tags/rel_WB_B3/
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7630d 08h /pci/tags/rel_WB_B3/
115 Added signals for WB Master B3. tadejm 7630d 08h /pci/tags/rel_WB_B3/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7637d 11h /pci/tags/rel_WB_B3/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7637d 16h /pci/tags/rel_WB_B3/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7639d 15h /pci/tags/rel_WB_B3/
109 There was missing path to hdl.var file. tadejm 7643d 13h /pci/tags/rel_WB_B3/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7643d 13h /pci/tags/rel_WB_B3/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7643d 13h /pci/tags/rel_WB_B3/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7648d 11h /pci/tags/rel_WB_B3/
105 Wrong pci_bridge32.v file included in the project! mihad 7653d 18h /pci/tags/rel_WB_B3/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7653d 21h /pci/tags/rel_WB_B3/
103 Added test application and modified files to support it. mihad 7700d 18h /pci/tags/rel_WB_B3/
102 Cleanup! mihad 7700d 18h /pci/tags/rel_WB_B3/
101 Added simulation files. mihad 7700d 18h /pci/tags/rel_WB_B3/
100 Cleanup! mihad 7700d 18h /pci/tags/rel_WB_B3/
99 Cleanup! mihad 7700d 19h /pci/tags/rel_WB_B3/
98 Cleanup. mihad 7700d 19h /pci/tags/rel_WB_B3/
97 Doing a little bit of cleanup. mihad 7700d 19h /pci/tags/rel_WB_B3/
96 Update! mihad 7700d 19h /pci/tags/rel_WB_B3/
95 Removed this file, because it was too large - long download time. mihad 7700d 19h /pci/tags/rel_WB_B3/
94 Changed one critical PCI bus signal logic. mihad 7700d 19h /pci/tags/rel_WB_B3/
93 Added a test application! mihad 7701d 02h /pci/tags/rel_WB_B3/
92 Update! mihad 7701d 03h /pci/tags/rel_WB_B3/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7736d 16h /pci/tags/rel_WB_B3/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7736d 16h /pci/tags/rel_WB_B3/
89 Burst 2 error fixed. mihad 7772d 17h /pci/tags/rel_WB_B3/

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