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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 62

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Rev Log message Author Age Path
62 Added BIST signals for RAMs. mihad 7933d 20h /pci/tags/rel_WB_B3/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7941d 20h /pci/tags/rel_WB_B3/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7941d 21h /pci/tags/rel_WB_B3/
58 Removed all logic from asynchronous reset network mihad 7946d 21h /pci/tags/rel_WB_B3/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7947d 03h /pci/tags/rel_WB_B3/
56 Number of state bits define was removed mihad 7947d 18h /pci/tags/rel_WB_B3/
55 Changed state machine encoding to true one-hot mihad 7947d 19h /pci/tags/rel_WB_B3/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7980d 20h /pci/tags/rel_WB_B3/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7981d 00h /pci/tags/rel_WB_B3/
52 Oops, never before noticed that OC header is missing mihad 7981d 04h /pci/tags/rel_WB_B3/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7981d 04h /pci/tags/rel_WB_B3/
50 Got rid of undef directives mihad 7983d 20h /pci/tags/rel_WB_B3/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7983d 20h /pci/tags/rel_WB_B3/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7983d 20h /pci/tags/rel_WB_B3/
47 Known issues repaired mihad 7984d 02h /pci/tags/rel_WB_B3/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7988d 20h /pci/tags/rel_WB_B3/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7990d 02h /pci/tags/rel_WB_B3/
44 Added for testing of Configuration Cycles Type 1 mihad 7990d 03h /pci/tags/rel_WB_B3/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7990d 03h /pci/tags/rel_WB_B3/
42 Removed out of date files mihad 8002d 03h /pci/tags/rel_WB_B3/
40 From these Wrod files PDF were created - added future improvements tadej 8080d 18h /pci/tags/rel_WB_B3/
39 File not needed tadej 8080d 18h /pci/tags/rel_WB_B3/
38 This file is not needed tadej 8080d 21h /pci/tags/rel_WB_B3/
37 These files are not needed any more tadej 8080d 21h /pci/tags/rel_WB_B3/
36 *** empty log message *** tadej 8080d 22h /pci/tags/rel_WB_B3/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8135d 06h /pci/tags/rel_WB_B3/
34 Added missing include statements mihad 8150d 04h /pci/tags/rel_WB_B3/
33 Added some testcases, removed un-needed fifo signals mihad 8151d 01h /pci/tags/rel_WB_B3/
32 Added include statement that was missing and causing errors mihad 8158d 22h /pci/tags/rel_WB_B3/
31 User defined constants used for Test Application tadej 8161d 17h /pci/tags/rel_WB_B3/

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