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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 69

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Rev	Log message	Author	Age	Path
69	Changed BIST signal names etc..	mihad	7933d 22h	/pci/tags/rel_WB_B3/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7937d 08h	/pci/tags/rel_WB_B3/
67	Changed BIST signals for RAMs.	tadejm	7937d 12h	/pci/tags/rel_WB_B3/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7940d 23h	/pci/tags/rel_WB_B3/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7943d 21h	/pci/tags/rel_WB_B3/
64	The testcase I just added in previous revision repaired	mihad	7943d 23h	/pci/tags/rel_WB_B3/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7944d 01h	/pci/tags/rel_WB_B3/
62	Added BIST signals for RAMs.	mihad	7946d 18h	/pci/tags/rel_WB_B3/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7954d 18h	/pci/tags/rel_WB_B3/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7954d 19h	/pci/tags/rel_WB_B3/
58	Removed all logic from asynchronous reset network	mihad	7959d 19h	/pci/tags/rel_WB_B3/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7960d 01h	/pci/tags/rel_WB_B3/
56	Number of state bits define was removed	mihad	7960d 16h	/pci/tags/rel_WB_B3/
55	Changed state machine encoding to true one-hot	mihad	7960d 17h	/pci/tags/rel_WB_B3/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7993d 18h	/pci/tags/rel_WB_B3/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7993d 22h	/pci/tags/rel_WB_B3/
52	Oops, never before noticed that OC header is missing	mihad	7994d 02h	/pci/tags/rel_WB_B3/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7994d 02h	/pci/tags/rel_WB_B3/
50	Got rid of undef directives	mihad	7996d 18h	/pci/tags/rel_WB_B3/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7996d 18h	/pci/tags/rel_WB_B3/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7996d 19h	/pci/tags/rel_WB_B3/
47	Known issues repaired	mihad	7997d 00h	/pci/tags/rel_WB_B3/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8001d 19h	/pci/tags/rel_WB_B3/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8003d 00h	/pci/tags/rel_WB_B3/
44	Added for testing of Configuration Cycles Type 1	mihad	8003d 01h	/pci/tags/rel_WB_B3/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	8003d 01h	/pci/tags/rel_WB_B3/
42	Removed out of date files	mihad	8015d 01h	/pci/tags/rel_WB_B3/
40	From these Wrod files PDF were created - added future improvements	tadej	8093d 16h	/pci/tags/rel_WB_B3/
39	File not needed	tadej	8093d 17h	/pci/tags/rel_WB_B3/
38	This file is not needed	tadej	8093d 19h	/pci/tags/rel_WB_B3/

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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 69

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