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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 78

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Rev	Log message	Author	Age	Path
78	Old files with wrong names removed.	mihad	7835d 13h	/pci/tags/rel_WB_B3/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7835d 13h	/pci/tags/rel_WB_B3/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7838d 12h	/pci/tags/rel_WB_B3/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7841d 13h	/pci/tags/rel_WB_B3/
73	Bug fixes, testcases added.	mihad	7841d 13h	/pci/tags/rel_WB_B3/
72	* empty log message *	mihad	7888d 17h	/pci/tags/rel_WB_B3/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7896d 09h	/pci/tags/rel_WB_B3/
69	Changed BIST signal names etc..	mihad	7933d 17h	/pci/tags/rel_WB_B3/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7937d 02h	/pci/tags/rel_WB_B3/
67	Changed BIST signals for RAMs.	tadejm	7937d 07h	/pci/tags/rel_WB_B3/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7940d 17h	/pci/tags/rel_WB_B3/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7943d 15h	/pci/tags/rel_WB_B3/
64	The testcase I just added in previous revision repaired	mihad	7943d 18h	/pci/tags/rel_WB_B3/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7943d 19h	/pci/tags/rel_WB_B3/
62	Added BIST signals for RAMs.	mihad	7946d 12h	/pci/tags/rel_WB_B3/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7954d 12h	/pci/tags/rel_WB_B3/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7954d 14h	/pci/tags/rel_WB_B3/
58	Removed all logic from asynchronous reset network	mihad	7959d 14h	/pci/tags/rel_WB_B3/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7959d 20h	/pci/tags/rel_WB_B3/
56	Number of state bits define was removed	mihad	7960d 10h	/pci/tags/rel_WB_B3/
55	Changed state machine encoding to true one-hot	mihad	7960d 11h	/pci/tags/rel_WB_B3/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7993d 13h	/pci/tags/rel_WB_B3/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7993d 16h	/pci/tags/rel_WB_B3/
52	Oops, never before noticed that OC header is missing	mihad	7993d 20h	/pci/tags/rel_WB_B3/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7993d 20h	/pci/tags/rel_WB_B3/
50	Got rid of undef directives	mihad	7996d 13h	/pci/tags/rel_WB_B3/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7996d 13h	/pci/tags/rel_WB_B3/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7996d 13h	/pci/tags/rel_WB_B3/
47	Known issues repaired	mihad	7996d 19h	/pci/tags/rel_WB_B3/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	8001d 13h	/pci/tags/rel_WB_B3/

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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 78

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