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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 83

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Rev Log message Author Age Path
83 Cleaned up the code. No functional changes. mihad 7854d 01h /pci/tags/rel_WB_B3/
81 Updated synchronization in top level fifo modules. mihad 7867d 22h /pci/tags/rel_WB_B3/
79 Updated. mihad 7871d 03h /pci/tags/rel_WB_B3/
78 Old files with wrong names removed. mihad 7871d 03h /pci/tags/rel_WB_B3/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7871d 03h /pci/tags/rel_WB_B3/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7874d 02h /pci/tags/rel_WB_B3/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7877d 03h /pci/tags/rel_WB_B3/
73 Bug fixes, testcases added. mihad 7877d 04h /pci/tags/rel_WB_B3/
72 *** empty log message *** mihad 7924d 07h /pci/tags/rel_WB_B3/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7931d 23h /pci/tags/rel_WB_B3/
69 Changed BIST signal names etc.. mihad 7969d 07h /pci/tags/rel_WB_B3/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7972d 16h /pci/tags/rel_WB_B3/
67 Changed BIST signals for RAMs. tadejm 7972d 21h /pci/tags/rel_WB_B3/
66 Changed empty status generation in pciw_fifo_control.v mihad 7976d 07h /pci/tags/rel_WB_B3/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7979d 05h /pci/tags/rel_WB_B3/
64 The testcase I just added in previous revision repaired mihad 7979d 08h /pci/tags/rel_WB_B3/
63 Added additional testcase and changed rst name in BIST to trst mihad 7979d 10h /pci/tags/rel_WB_B3/
62 Added BIST signals for RAMs. mihad 7982d 02h /pci/tags/rel_WB_B3/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7990d 02h /pci/tags/rel_WB_B3/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7990d 04h /pci/tags/rel_WB_B3/
58 Removed all logic from asynchronous reset network mihad 7995d 04h /pci/tags/rel_WB_B3/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7995d 10h /pci/tags/rel_WB_B3/
56 Number of state bits define was removed mihad 7996d 01h /pci/tags/rel_WB_B3/
55 Changed state machine encoding to true one-hot mihad 7996d 01h /pci/tags/rel_WB_B3/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8029d 03h /pci/tags/rel_WB_B3/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8029d 06h /pci/tags/rel_WB_B3/
52 Oops, never before noticed that OC header is missing mihad 8029d 10h /pci/tags/rel_WB_B3/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8029d 11h /pci/tags/rel_WB_B3/
50 Got rid of undef directives mihad 8032d 03h /pci/tags/rel_WB_B3/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8032d 03h /pci/tags/rel_WB_B3/

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