OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] - Rev 91

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7729d 18h /pci/tags/rel_WB_B3/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7729d 18h /pci/tags/rel_WB_B3/
89 Burst 2 error fixed. mihad 7765d 18h /pci/tags/rel_WB_B3/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7771d 17h /pci/tags/rel_WB_B3/
87 Updated acording to RTL changes. mihad 7783d 15h /pci/tags/rel_WB_B3/
86 Entered the option to disable no response counter in wb master. mihad 7783d 15h /pci/tags/rel_WB_B3/
85 Changed Vendor ID defines. mihad 7783d 19h /pci/tags/rel_WB_B3/
84 Changed vendor ID. mihad 7787d 13h /pci/tags/rel_WB_B3/
83 Cleaned up the code. No functional changes. mihad 7812d 12h /pci/tags/rel_WB_B3/
81 Updated synchronization in top level fifo modules. mihad 7826d 08h /pci/tags/rel_WB_B3/
79 Updated. mihad 7829d 13h /pci/tags/rel_WB_B3/
78 Old files with wrong names removed. mihad 7829d 14h /pci/tags/rel_WB_B3/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7829d 14h /pci/tags/rel_WB_B3/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7832d 13h /pci/tags/rel_WB_B3/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7835d 14h /pci/tags/rel_WB_B3/
73 Bug fixes, testcases added. mihad 7835d 14h /pci/tags/rel_WB_B3/
72 *** empty log message *** mihad 7882d 18h /pci/tags/rel_WB_B3/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7890d 10h /pci/tags/rel_WB_B3/
69 Changed BIST signal names etc.. mihad 7927d 17h /pci/tags/rel_WB_B3/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7931d 03h /pci/tags/rel_WB_B3/
67 Changed BIST signals for RAMs. tadejm 7931d 08h /pci/tags/rel_WB_B3/
66 Changed empty status generation in pciw_fifo_control.v mihad 7934d 18h /pci/tags/rel_WB_B3/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7937d 16h /pci/tags/rel_WB_B3/
64 The testcase I just added in previous revision repaired mihad 7937d 18h /pci/tags/rel_WB_B3/
63 Added additional testcase and changed rst name in BIST to trst mihad 7937d 20h /pci/tags/rel_WB_B3/
62 Added BIST signals for RAMs. mihad 7940d 13h /pci/tags/rel_WB_B3/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7948d 13h /pci/tags/rel_WB_B3/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7948d 14h /pci/tags/rel_WB_B3/
58 Removed all logic from asynchronous reset network mihad 7953d 15h /pci/tags/rel_WB_B3/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7953d 20h /pci/tags/rel_WB_B3/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.