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[/] [pci/] [tags/] [rel_WB_B3/] [rtl/] - Rev 121

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Rev	Log message	Author	Age	Path
121	This commit was manufactured by cvs2svn to create tag 'rel_WB_B3'.		7616d 13h	/pci/tags/rel_WB_B3/rtl/
117	WB Master is now WISHBONE B3 compatible.	tadejm	7616d 13h	/pci/tags/rel_WB_B3/rtl/
116	Corrected bug when writing to FIFO (now it is registered).	tadejm	7616d 13h	/pci/tags/rel_WB_B3/rtl/
115	Added signals for WB Master B3.	tadejm	7616d 13h	/pci/tags/rel_WB_B3/rtl/
113	ifdefs moved to thier own lines, this confuses some of the tools.	simons	7623d 16h	/pci/tags/rel_WB_B3/rtl/
111	synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.	simons	7623d 21h	/pci/tags/rel_WB_B3/rtl/
110	Module that converts slave WISHBONE B3 accesses to WISHBONE B2 accesses with CAB.	mihad	7625d 20h	/pci/tags/rel_WB_B3/rtl/
108	Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.	tadejm	7629d 17h	/pci/tags/rel_WB_B3/rtl/
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7634d 16h	/pci/tags/rel_WB_B3/rtl/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7640d 02h	/pci/tags/rel_WB_B3/rtl/
94	Changed one critical PCI bus signal logic.	mihad	7687d 00h	/pci/tags/rel_WB_B3/rtl/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7764d 21h	/pci/tags/rel_WB_B3/rtl/
86	Entered the option to disable no response counter in wb master.	mihad	7776d 19h	/pci/tags/rel_WB_B3/rtl/
83	Cleaned up the code. No functional changes.	mihad	7805d 16h	/pci/tags/rel_WB_B3/rtl/
81	Updated synchronization in top level fifo modules.	mihad	7819d 12h	/pci/tags/rel_WB_B3/rtl/
79	Updated.	mihad	7822d 17h	/pci/tags/rel_WB_B3/rtl/
78	Old files with wrong names removed.	mihad	7822d 17h	/pci/tags/rel_WB_B3/rtl/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7822d 17h	/pci/tags/rel_WB_B3/rtl/
73	Bug fixes, testcases added.	mihad	7828d 18h	/pci/tags/rel_WB_B3/rtl/
72	* empty log message *	mihad	7875d 22h	/pci/tags/rel_WB_B3/rtl/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7883d 13h	/pci/tags/rel_WB_B3/rtl/
69	Changed BIST signal names etc..	mihad	7920d 21h	/pci/tags/rel_WB_B3/rtl/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7924d 06h	/pci/tags/rel_WB_B3/rtl/
67	Changed BIST signals for RAMs.	tadejm	7924d 11h	/pci/tags/rel_WB_B3/rtl/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7927d 22h	/pci/tags/rel_WB_B3/rtl/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7930d 20h	/pci/tags/rel_WB_B3/rtl/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7931d 00h	/pci/tags/rel_WB_B3/rtl/
62	Added BIST signals for RAMs.	mihad	7933d 17h	/pci/tags/rel_WB_B3/rtl/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7941d 17h	/pci/tags/rel_WB_B3/rtl/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7941d 18h	/pci/tags/rel_WB_B3/rtl/

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[/] [pci/] [tags/] [rel_WB_B3/] [rtl/] - Rev 121

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