URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] [sim/] - Rev 104

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7637d 14h	/pci/tags/rel_WB_B3/sim/
95	Removed this file, because it was too large - long download time.	mihad	7684d 12h	/pci/tags/rel_WB_B3/sim/
92	Update!	mihad	7684d 19h	/pci/tags/rel_WB_B3/sim/
81	Updated synchronization in top level fifo modules.	mihad	7817d 00h	/pci/tags/rel_WB_B3/sim/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7820d 05h	/pci/tags/rel_WB_B3/sim/
73	Bug fixes, testcases added.	mihad	7826d 06h	/pci/tags/rel_WB_B3/sim/
72	* empty log message *	mihad	7873d 10h	/pci/tags/rel_WB_B3/sim/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7928d 12h	/pci/tags/rel_WB_B3/sim/
62	Added BIST signals for RAMs.	mihad	7931d 05h	/pci/tags/rel_WB_B3/sim/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7939d 05h	/pci/tags/rel_WB_B3/sim/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7939d 06h	/pci/tags/rel_WB_B3/sim/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7978d 13h	/pci/tags/rel_WB_B3/sim/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7981d 05h	/pci/tags/rel_WB_B3/sim/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7987d 11h	/pci/tags/rel_WB_B3/sim/
42	Removed out of date files	mihad	7999d 12h	/pci/tags/rel_WB_B3/sim/
30	Example of PCI testbench log file	mihad	8159d 10h	/pci/tags/rel_WB_B3/sim/
27	Modified testbench and fixed some bugs	mihad	8162d 05h	/pci/tags/rel_WB_B3/sim/
26	Modified testbench and fixed some bugs	mihad	8162d 05h	/pci/tags/rel_WB_B3/sim/
22	Added short description for simulation running	mihad	8180d 06h	/pci/tags/rel_WB_B3/sim/
20	* empty log message *	mihad	8180d 07h	/pci/tags/rel_WB_B3/sim/
17	* empty log message *	mihad	8180d 08h	/pci/tags/rel_WB_B3/sim/
16	Import of various scripts for simulation running	mihad	8180d 08h	/pci/tags/rel_WB_B3/sim/
3	New project directory structure	mihad	8302d 06h	/pci/tags/rel_WB_B3/sim/

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] [sim/] - Rev 104

Filtering Options