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[/] [pci/] [tags/] [rel_WB_B3/] [sim/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5568d 16h /pci/tags/rel_WB_B3/sim/
121 This commit was manufactured by cvs2svn to create tag 'rel_WB_B3'. 7596d 03h /pci/tags/rel_WB_B3/sim/
118 Some minor changes due to changes in core. tadejm 7596d 03h /pci/tags/rel_WB_B3/sim/
109 There was missing path to hdl.var file. tadejm 7609d 07h /pci/tags/rel_WB_B3/sim/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7614d 06h /pci/tags/rel_WB_B3/sim/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7619d 16h /pci/tags/rel_WB_B3/sim/
95 Removed this file, because it was too large - long download time. mihad 7666d 14h /pci/tags/rel_WB_B3/sim/
92 Update! mihad 7666d 21h /pci/tags/rel_WB_B3/sim/
81 Updated synchronization in top level fifo modules. mihad 7799d 02h /pci/tags/rel_WB_B3/sim/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7802d 07h /pci/tags/rel_WB_B3/sim/
73 Bug fixes, testcases added. mihad 7808d 08h /pci/tags/rel_WB_B3/sim/
72 *** empty log message *** mihad 7855d 12h /pci/tags/rel_WB_B3/sim/
63 Added additional testcase and changed rst name in BIST to trst mihad 7910d 14h /pci/tags/rel_WB_B3/sim/
62 Added BIST signals for RAMs. mihad 7913d 07h /pci/tags/rel_WB_B3/sim/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7921d 07h /pci/tags/rel_WB_B3/sim/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7921d 08h /pci/tags/rel_WB_B3/sim/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7960d 15h /pci/tags/rel_WB_B3/sim/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7963d 07h /pci/tags/rel_WB_B3/sim/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7969d 13h /pci/tags/rel_WB_B3/sim/
42 Removed out of date files mihad 7981d 14h /pci/tags/rel_WB_B3/sim/
30 Example of PCI testbench log file mihad 8141d 12h /pci/tags/rel_WB_B3/sim/
27 Modified testbench and fixed some bugs mihad 8144d 07h /pci/tags/rel_WB_B3/sim/
26 Modified testbench and fixed some bugs mihad 8144d 07h /pci/tags/rel_WB_B3/sim/
22 Added short description for simulation running mihad 8162d 08h /pci/tags/rel_WB_B3/sim/
20 *** empty log message *** mihad 8162d 09h /pci/tags/rel_WB_B3/sim/
17 *** empty log message *** mihad 8162d 10h /pci/tags/rel_WB_B3/sim/
16 Import of various scripts for simulation running mihad 8162d 10h /pci/tags/rel_WB_B3/sim/
3 New project directory structure mihad 8284d 08h /pci/tags/rel_WB_B3/sim/

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