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[/] [pci/] [trunk/] [bench/] [verilog/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5568d 04h /pci/trunk/bench/verilog/
152 Some regression tests were failing during completion expired testing. mihad 7003d 22h /pci/trunk/bench/verilog/
151 Top now sends x's to inputs when output is enabled. mihad 7196d 22h /pci/trunk/bench/verilog/
148 Changed minimum pci image size to 256 bytes because
of some PC system problems with size of IO images.		 mihad 7231d 21h /pci/trunk/bench/verilog/
143 Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines.
Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers.		 mihad 7274d 23h /pci/trunk/bench/verilog/
142 Single PCI Master write fix. mihad 7384d 20h /pci/trunk/bench/verilog/
140 Update! SPOCI Implemented! mihad 7440d 00h /pci/trunk/bench/verilog/
139 Added for SPOCI testing! mihad 7440d 00h /pci/trunk/bench/verilog/
138 added test_initial_all_conf_values
mbist_ctrl_i replaced by mbist_en_i		 fr2201 7456d 19h /pci/trunk/bench/verilog/
137 def_wb_imagex_addr_map defined correctly fr2201 7467d 02h /pci/trunk/bench/verilog/
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7476d 01h /pci/trunk/bench/verilog/
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.		 mihad 7480d 00h /pci/trunk/bench/verilog/
122 mbist signals updated according to newest convention markom 7539d 03h /pci/trunk/bench/verilog/
119 Added support for WB B3. Some testcases were updated. tadejm 7595d 15h /pci/trunk/bench/verilog/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7608d 20h /pci/trunk/bench/verilog/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7613d 18h /pci/trunk/bench/verilog/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7619d 04h /pci/trunk/bench/verilog/
92 Update! mihad 7666d 10h /pci/trunk/bench/verilog/
89 Burst 2 error fixed. mihad 7738d 00h /pci/trunk/bench/verilog/
87 Updated acording to RTL changes. mihad 7755d 21h /pci/trunk/bench/verilog/
81 Updated synchronization in top level fifo modules. mihad 7798d 14h /pci/trunk/bench/verilog/
73 Bug fixes, testcases added. mihad 7807d 20h /pci/trunk/bench/verilog/
69 Changed BIST signal names etc.. mihad 7899d 23h /pci/trunk/bench/verilog/
66 Changed empty status generation in pciw_fifo_control.v mihad 7907d 00h /pci/trunk/bench/verilog/
64 The testcase I just added in previous revision repaired mihad 7910d 00h /pci/trunk/bench/verilog/
63 Added additional testcase and changed rst name in BIST to trst mihad 7910d 02h /pci/trunk/bench/verilog/
62 Added BIST signals for RAMs. mihad 7912d 19h /pci/trunk/bench/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7926d 02h /pci/trunk/bench/verilog/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7959d 19h /pci/trunk/bench/verilog/
52 Oops, never before noticed that OC header is missing mihad 7960d 03h /pci/trunk/bench/verilog/

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