| Rev |
Log message |
Author |
Age |
Path |
| 154 |
New directory structure. |
root |
5572d 02h |
/pci/trunk/rtl/ |
| 153 |
Write burst performance patch applied.
Not tested. Everything should be backwards
compatible, since functional code is ifdefed. |
mihad |
6551d 21h |
/trunk/rtl/ |
| 150 |
The control inputs from PCI are now muxed with control outputs
using output enable state for given signal. |
mihad |
7200d 21h |
/trunk/rtl/ |
| 149 |
Removed some unused signals. |
mihad |
7235d 18h |
/trunk/rtl/ |
| 148 |
Changed minimum pci image size to 256 bytes because
of some PC system problems with size of IO images. |
mihad |
7235d 19h |
/trunk/rtl/ |
| 147 |
Removed unsinthesizable !== comparation. |
mihad |
7239d 01h |
/trunk/rtl/ |
| 143 |
Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines.
Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers. |
mihad |
7278d 22h |
/trunk/rtl/ |
| 142 |
Single PCI Master write fix. |
mihad |
7388d 18h |
/trunk/rtl/ |
| 140 |
Update! SPOCI Implemented! |
mihad |
7443d 23h |
/trunk/rtl/ |
| 137 |
def_wb_imagex_addr_map defined correctly |
fr2201 |
7471d 01h |
/trunk/rtl/ |
| 136 |
Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO) |
fr2201 |
7471d 01h |
/trunk/rtl/ |
| 132 |
Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles. |
mihad |
7479d 23h |
/trunk/rtl/ |
| 131 |
Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly. |
mihad |
7483d 22h |
/trunk/rtl/ |
| 130 |
The wbs B3 to B2 translation logic had wrong reset wire connected! |
mihad |
7488d 22h |
/trunk/rtl/ |
| 128 |
Some warning cleanup. |
simons |
7490d 01h |
/trunk/rtl/ |
| 126 |
ifdef - endif statements put in separate lines for flint compatibility. |
simons |
7497d 18h |
/trunk/rtl/ |
| 124 |
Added missing signals to 2 sensitivity lists. Everything works the same as before. |
tadejm |
7536d 01h |
/trunk/rtl/ |
| 122 |
mbist signals updated according to newest convention |
markom |
7543d 01h |
/trunk/rtl/ |
| 117 |
WB Master is now WISHBONE B3 compatible. |
tadejm |
7599d 14h |
/trunk/rtl/ |
| 116 |
Corrected bug when writing to FIFO (now it is registered). |
tadejm |
7599d 14h |
/trunk/rtl/ |
| 115 |
Added signals for WB Master B3. |
tadejm |
7599d 14h |
/trunk/rtl/ |
| 113 |
ifdefs moved to thier own lines, this confuses some of the tools. |
simons |
7606d 16h |
/trunk/rtl/ |
| 111 |
synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. |
simons |
7606d 21h |
/trunk/rtl/ |
| 110 |
Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB. |
mihad |
7608d 20h |
/trunk/rtl/ |
| 108 |
Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. |
tadejm |
7612d 18h |
/trunk/rtl/ |
| 106 |
Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet. |
mihad |
7617d 16h |
/trunk/rtl/ |
| 104 |
Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs. |
mihad |
7623d 02h |
/trunk/rtl/ |
| 94 |
Changed one critical PCI bus signal logic. |
mihad |
7670d 00h |
/trunk/rtl/ |
| 88 |
Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos. |
mihad |
7747d 21h |
/trunk/rtl/ |
| 86 |
Entered the option to disable no response counter in wb master. |
mihad |
7759d 19h |
/trunk/rtl/ |
