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Rev Log message Author Age Path
352 linus 5571d 12h /plasma/tags/V3_0/
350 root 5600d 08h /plasma/tags/V3_0/
140 This commit was manufactured by cvs2svn to create tag 'V3_0'. 6700d 20h /plasma/tags/V3_0/
139 Major changes -- updated to Plasma Version 3 rhoads 6700d 20h /plasma/tags/V3_0/
138 Realtime Operating System: Updated to Plasma Version 3 rhoads 6700d 20h /plasma/tags/V3_0/
137 Updated to Plasma Version 3 rhoads 6700d 20h /plasma/tags/V3_0/
136 Better setting of $GP register rhoads 6700d 20h /plasma/tags/V3_0/
135 Added lots of spaces rhoads 7041d 20h /plasma/tags/V3_0/
134 Added lots of spaces rhoads 7041d 20h /plasma/tags/V3_0/
133 Fixed bug when MIPS executable compiled under Linux. Added lots of spaces rhoads 7041d 21h /plasma/tags/V3_0/
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7180d 19h /plasma/tags/V3_0/
131 Changed "GENERIC" to "DEFAULT" to be Xilinx friendly. rhoads 7180d 19h /plasma/tags/V3_0/
130 Added better spacing rhoads 7180d 19h /plasma/tags/V3_0/
129 Added reset_in to sensitivity list rhoads 7199d 19h /plasma/tags/V3_0/
128 Reset all registers, constants now upper case. rhoads 7318d 06h /plasma/tags/V3_0/
126 Added note that CC is for x86 and gmake has problems with MIPS gcc libraries. rhoads 7336d 19h /plasma/tags/V3_0/
125 Fixed pc_source_type comment. rhoads 7336d 19h /plasma/tags/V3_0/
124 Holger Lohn's fix for interrupts when 3-state pipeline enabled. rhoads 7336d 19h /plasma/tags/V3_0/
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7403d 20h /plasma/tags/V3_0/
122 Added comment to explain why c_bus isn't delayed but reg_dest is delayed. rhoads 7467d 20h /plasma/tags/V3_0/
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7479d 09h /plasma/tags/V3_0/
120 Make generics "GENERIC" rhoads 7479d 09h /plasma/tags/V3_0/
119 Opcodes from count.c rhoads 7517d 20h /plasma/tags/V3_0/
118 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7517d 20h /plasma/tags/V3_0/
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7517d 20h /plasma/tags/V3_0/
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7517d 20h /plasma/tags/V3_0/
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7517d 20h /plasma/tags/V3_0/
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7517d 20h /plasma/tags/V3_0/
113 Matthias Grunewald's bug fixes:
Branch and compare instructions didn't interpret immediate as signed.		 rhoads 7517d 20h /plasma/tags/V3_0/
112 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7517d 20h /plasma/tags/V3_0/

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